公开(公告)号：US06537417B2

公开(公告)日：2003-03-25

申请号：US09985308

申请日：2001-11-02

申请人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

发明人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

IPC分类号： H01L213065

CPC分类号： H01L21/32136 ,  C23F4/00 ,  H01J37/185 ,  H01L21/67017 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67161 ,  H01L21/67207 ,  H01L21/67745 ,  H01L21/67751

摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

公开(公告)号：US6036816A

公开(公告)日：2000-03-14

申请号：US470442

申请日：1995-06-06

申请人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

发明人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

IPC分类号： C23F4/00 ,  H01J37/18 ,  H01L21/00 ,  H01L21/3213 ,  H01L21/461 ,  H01L21/677 ,  H01L21/306

CPC分类号： H01L21/32136 ,  C23F4/00 ,  H01J37/185 ,  H01L21/67017 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67161 ,  H01L21/67207 ,  H01L21/67745 ,  H01L21/67751

摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

摘要翻译： 公开了用于处理样品的装置以及使用该装置的方法。 该设备包括用于处理样品（例如，等离子体蚀刻设备）的处理设备（a），（b）用于除去由样品处理形成的残余腐蚀性化合物，（c）用于湿法处理样品和（d）干燥 处理样品。 可以进行多个样品的湿法处理。 湿式处理装置可以包括多个湿加工站。 样品可以通过多个湿处理站串联通过，或者可以通过湿处理站并行通过。

公开(公告)号：US5661061A

公开(公告)日：1997-08-26

申请号：US411149

申请日：1995-03-27

申请人： Hirohisa Usuami ,  Kazuyuki Tsunokuni ,  Masayuki Kojima ,  Kazuo Nojiri ,  Keiji Okamoto

发明人： Hirohisa Usuami ,  Kazuyuki Tsunokuni ,  Masayuki Kojima ,  Kazuo Nojiri ,  Keiji Okamoto

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A process for forming an upper-layer fin and a lower-layer fin of a storage electrode, and a semiconductor integrated circuit device fabricated by the process. When two-layered polycrystalline silicon films are to be sequentially etched to form the upper-layer fin and the lower-layer fin by the dry-etching method using a first mask, the upper polycrystalline silicon film is patterned at first so far as to form the clearance of the upper-layer fins with the minimum working size of the memory cells of a DRAM, to form the upper-layer fin. Next, the lower-layer fin is formed by the dry-etching method using a second mask which has a pattern enlarged in self-alignment from the pattern of the first mask, so that it is given a larger horizontal size than that of the upper-layer fin.

摘要翻译： 一种用于形成存储电极的上层翅片和下层翅片的方法，以及通过该方法制造的半导体集成电路器件。 当通过使用第一掩模的干蚀刻方法顺序蚀刻两层多晶硅膜以形成上层翅片和下层翅片时，首先将上多晶硅膜图案化以形成 以DRAM的存储单元的最小工作尺寸的上层翅片的间隙形成上层翅片。 接下来，通过使用具有从第一掩模的图案自对准的图案放大的图案的第二掩模的干法蚀刻法形成下层翅片，使得其具有比上部的图案更大的水平尺寸 层翅

公开(公告)号：US06509277B1

公开(公告)日：2003-01-21

申请号：US09664381

申请日：2000-09-18

申请人： Masayoshi Saito ,  Katsuhiko Hotta ,  Masayoshi Hirasawa ,  Masayuki Kojima ,  Hiroyuki Uchiyama ,  Hiroyuki Maruyama ,  Takuya Fukuda

发明人： Masayoshi Saito ,  Katsuhiko Hotta ,  Masayoshi Hirasawa ,  Masayuki Kojima ,  Hiroyuki Uchiyama ,  Hiroyuki Maruyama ,  Takuya Fukuda

IPC分类号： H01L21302

CPC分类号： H01L21/3124 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3125 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L27/10814 ,  H01L27/10894

摘要： An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode 9 of a MISFET (Qs, Qn, Qp). A polysilazan SOG film 57 not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).

摘要翻译： 使用通过在约800℃的高温下热处理聚硅氮烷型SOG膜获得的SOG膜16作为形成在MISFET（Qs，Qn，Qp）的栅极9上的平坦化绝缘膜。 不进行这种热处理的聚硅氮烷SOG膜57被用作布置在上部布线层（54,55,56,62,63）之间的层间绝缘膜。

公开(公告)号：US06833331B2

公开(公告)日：2004-12-21

申请号：US10303935

申请日：2002-11-26

申请人： Masayoshi Saito ,  Katsuhiko Hotta ,  Masayoshi Hirasawa ,  Masayuki Kojima ,  Hiroyuki Uchiyama ,  Hiroyuki Maruyama ,  Takuya Fukuda

发明人： Masayoshi Saito ,  Katsuhiko Hotta ,  Masayoshi Hirasawa ,  Masayuki Kojima ,  Hiroyuki Uchiyama ,  Hiroyuki Maruyama ,  Takuya Fukuda

IPC分类号： H01L2131

CPC分类号： H01L21/3124 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3125 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L27/10814 ,  H01L27/10894

摘要： An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode (9; see FIGS. 31 and 32) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film (57) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).

摘要翻译： 使用通过在约800℃的高温下热处理聚硅氮烷型SOG膜获得的SOG膜16作为形成在MISFET的栅极（9;参见图31和32）上的平坦化绝缘膜） （Qs，Qn，Qp）将不进行这种热处理的聚硅氮烷SOG膜（57）用作布置在上布线层（54,55,56,62,63）中的层间绝缘膜。

公开(公告)号：US20100132392A1

公开(公告)日：2010-06-03

申请号：US12095107

申请日：2006-11-26

申请人： Masanao Yasutomi ,  Masayuki Kojima ,  Masuzou Takahashi ,  Toshihiro Wakamatsu

发明人： Masanao Yasutomi ,  Masayuki Kojima ,  Masuzou Takahashi ,  Toshihiro Wakamatsu

IPC分类号： F25D21/14 ,  F25D17/06

CPC分类号： F24F1/0007 ,  F24F1/0025 ,  F24F13/222

摘要： Grooves are formed on a back surface 22 of a tongue part 21 of a rear plate 3 which surface does not guide a flow of air.

摘要翻译： 凹槽形成在后板3的舌部21的后表面22上，该表面不引导空气流。

公开(公告)号：US06838388B2

公开(公告)日：2005-01-04

申请号：US09893577

申请日：2001-06-29

申请人： Masahiro Tadokoro ,  Masahiro Shioya ,  Masayuki Kojima ,  Takenobu Ikeda

发明人： Masahiro Tadokoro ,  Masahiro Shioya ,  Masayuki Kojima ,  Takenobu Ikeda

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10855 ,  H01L27/10888

摘要： A fabrication method of a semiconductor integrated circuit device comprises, in an SAC process or HARC process, subjecting a semiconductor substrate to plasma etching to make contact holes in an oxide film made of a silicon oxide film formed on the semiconductor substrate. For improving the ease-in-etching property of the silicon oxide film and selectivity to a nitride film, a residence time of an etching gas within a chamber is so set as to be in a range where selectivity to an insulating film made of silicon nitride is improved by using etching conditions of a low pressure and a large flow rate of the etching gas of C5H8/O2/Ar.

公开(公告)号：US5754915A

公开(公告)日：1998-05-19

申请号：US750676

申请日：1996-12-13

申请人： Shigeru Masuda ,  Tsukasa Nakano ,  Masayuki Kojima ,  Masayuki Nakanishi ,  Toshihiko Nakano ,  Haruo Hakamada ,  Hideo Ishii

发明人： Shigeru Masuda ,  Tsukasa Nakano ,  Masayuki Kojima ,  Masayuki Nakanishi ,  Toshihiko Nakano ,  Haruo Hakamada ,  Hideo Ishii

IPC分类号： G03D3/06

CPC分类号： G03D3/065

摘要： An automatic photosensitive material developing machine supplies a solid processing solution to be dissolved according to consumption of processing solution for a silver halide photosensitive material to be treated. The developing machine includes a solid processing solution supplying section for supplying the solid processing solution from a solid processing solution cartridge containing the solid processing solution, and a solid processing solution transferring section for receiving the solid processing solution supplied by the solid processing solution supplying section in a bucket, and for transferring the bucket upward.

摘要翻译： PCT No.PCT / JP95 / 01188 Sec。 371日期1996年12月13日第 102（e）日期1996年12月13日PCT提交1995年6月12日PCT公布。 WO95 / 34844 PCT出版物 日期1995年12月21日自动感光材料显影机根据消费用于待处理的卤化银感光材料的处理溶液提供待溶解的固体处理溶液。 显影机包括：固体处理剂供给部，用于从固体处理溶液的固体处理液筒供给固体处理液;固体处理液转移部，其用于接收由固体处理剂供给部供给的固体处理液 一个铲斗，并将铲斗向上传送。

公开(公告)号：US5475463A

公开(公告)日：1995-12-12

申请号：US219935

申请日：1994-03-30

申请人： Takuji Yamaguchi ,  Tohgo Kinoshita ,  Yasunobu Shimamura ,  Yuji Yamazoe ,  Shinji Fukushima ,  Masayuki Kojima

发明人： Takuji Yamaguchi ,  Tohgo Kinoshita ,  Yasunobu Shimamura ,  Yuji Yamazoe ,  Shinji Fukushima ,  Masayuki Kojima

IPC分类号： G03D3/13 ,  G03D13/00 ,  G03D3/08

CPC分类号： G03D13/003 ,  G03D3/135

摘要： Various arrangements are proposed for coupling films to a leader. A hole is formed in one of the films and the leader to receive a tab which is formed on the other. These arrangements allow stable coupling of the films to the leader and easy uncoupling. They eliminate the use of splice tape.

摘要翻译： 提出了将膜耦合到引导件的各种布置。 在一个膜和引导件中形成孔，以接收在另一个上形成的突片。 这些布置允许膜稳定地连接到引导件并且易于解耦。 它们消除了使用拼接胶带。

公开(公告)号：US5445709A

公开(公告)日：1995-08-29

申请号：US154566

申请日：1993-11-19

申请人： Masayuki Kojima ,  Yoshikazu Ito ,  Kazuhsi Tomita ,  Shigeki Tozawa ,  Shunichi Iimuro ,  Masashi Arasawa ,  Eiichi Nishimura

发明人： Masayuki Kojima ,  Yoshikazu Ito ,  Kazuhsi Tomita ,  Shigeki Tozawa ,  Shunichi Iimuro ,  Masashi Arasawa ,  Eiichi Nishimura

IPC分类号： C23F4/00 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/06

CPC分类号： H01J37/32009 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32532 ,  H01J37/32541 ,  H01J37/32724 ,  H01J2237/3345

摘要： A parallel-plate plasma etching apparatus includes a susceptor electrode and a shower electrode which are arranged in a process chamber. A semiconductor wafer is placed on the susceptor electrode. A shower region defined by a plurality of process gas supply holes is formed in the shower electrode. The shower electrode is cooled by a cooling block and causes an effective electrode portion of the shower electrode to have a temperature gradient such that a temperature at the central portion of the effective electrode portion is lower than a temperature at the peripheral portion of the effective electrode portion. The diameter of the shower region is selected to be smaller than the diameter of the wafer by 5 to 25% such that degradation of planar uniformity of a degree of etching anisotropy on the wafer caused by the temperature gradient of the effective electrode portion is compensated for. The diameter of the effective electrode portion is selected to be larger than the size of a wafer by 5 to 35% such that a taper angle of a side wall to be etched formed by etching is set to be 85.degree. to 90.degree..

摘要翻译： 平行板等离子体蚀刻装置包括布置在处理室中的基座电极和淋浴电极。 将半导体晶片放置在基座电极上。 在淋浴电极中形成由多个处理气体供给孔限定的淋浴区域。 淋浴电极被冷却块冷却，使淋浴电极的有效电极部分具有温度梯度，使得有效电极部分的中心部分的温度低于有效电极周边部分的温度 一部分。 淋浴区域的直径被选择为小于晶片的直径5至25％，使得由有效电极部分的温度梯度引起的晶片上的蚀刻各向异性程度的平面均匀度的降低被补偿 。 选择有效电极部分的直径大于晶片的尺寸5至35％，使得通过蚀刻形成的待蚀刻侧壁的锥角设定为85°至90°。