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公开(公告)号:US12029031B2
公开(公告)日:2024-07-02
申请号:US18314527
申请日:2023-05-09
Applicant: KIOXIA CORPORATION
Inventor: Takehiko Amaki , Yoshihisa Kojima , Toshikatsu Hida , Marie Grace Izabelle Angeles Sia , Riki Suzuki , Shohei Asami
IPC: H10B41/27 , G11C7/04 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , H10B43/27 , H10B43/35
CPC classification number: H10B41/27 , G11C7/04 , G11C16/0483 , G11C16/08 , G11C16/107 , G11C16/16 , G11C16/26 , H10B43/27 , H10B43/35
Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
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公开(公告)号:US11893237B2
公开(公告)日:2024-02-06
申请号:US17591812
申请日:2022-02-03
Applicant: Kioxia Corporation
Inventor: Kazuya Kitsunai , Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Junji Yano
CPC classification number: G06F3/0604 , G06F3/064 , G06F3/0616 , G06F3/0619 , G06F3/0647 , G06F3/0652 , G06F3/0659 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F2212/1036 , G06F2212/7202 , G06F2212/7205 , G06F2212/7211
Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
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公开(公告)号:US11699499B2
公开(公告)日:2023-07-11
申请号:US17187705
申请日:2021-02-26
Applicant: KIOXIA CORPORATION
Inventor: Tsukasa Tokutomi , Kiwamu Watanabe , Riki Suzuki , Toshikatsu Hida , Takahiro Onagi
CPC classification number: G11C29/42 , G11C29/24 , G11C29/44 , G11C2029/1202
Abstract: According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m−1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.
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24.
公开(公告)号:US11657875B2
公开(公告)日:2023-05-23
申请号:US17849062
申请日:2022-06-24
Applicant: KIOXIA CORPORATION
Inventor: Suguru Nishikawa , Yoshihisa Kojima , Riki Suzuki , Masanobu Shirakawa , Toshikatsu Hida
IPC: G06F12/00 , G11C16/10 , G11C16/04 , G11C16/14 , G06F3/06 , G11C11/56 , G11C16/08 , G11C16/34 , G11C29/02 , G11C29/42 , G11C16/32 , H01L27/1157 , H01L27/11582
CPC classification number: G11C16/10 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/14 , G11C16/32 , G11C16/349 , G11C16/3459 , G11C16/3495 , G11C29/021 , G11C29/028 , G11C29/42 , G11C11/5671 , H01L27/1157 , H01L27/11582
Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
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公开(公告)号:US11442808B2
公开(公告)日:2022-09-13
申请号:US17198451
申请日:2021-03-11
Applicant: Kioxia Corporation
Inventor: Takehiko Amaki , Toshikatsu Hida , Shunichi Igahara , Yoshihisa Kojima , Suguru Nishikawa
IPC: G11C29/00 , G06F11/10 , G06F12/0891 , G06F12/02 , G06F11/07
Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n−1 data portions of a first unit that are included in n−1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n−1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n−1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.
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公开(公告)号:US11436136B2
公开(公告)日:2022-09-06
申请号:US16807275
申请日:2020-03-03
Applicant: Kioxia Corporation
Inventor: Takehiko Amaki , Toshikatsu Hida , Shunichi Igahara , Yoshihisa Kojima , Suguru Nishikawa
Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.
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公开(公告)号:US11287975B2
公开(公告)日:2022-03-29
申请号:US16730329
申请日:2019-12-30
Applicant: KIOXIA CORPORATION
Inventor: Kazuya Kitsunai , Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Junji Yano
Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
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公开(公告)号:US12086439B2
公开(公告)日:2024-09-10
申请号:US18343835
申请日:2023-06-29
Applicant: KIOXIA CORPORATION
Inventor: Shunichi Igahara , Toshikatsu Hida , Riki Suzuki , Takehiko Amaki , Suguru Nishikawa , Yoshihisa Kojima
CPC classification number: G06F3/0634 , G06F3/0604 , G06F3/061 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F12/0253 , G06F12/10 , G06F2212/1044 , G06F2212/657
Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.
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公开(公告)号:US11874738B2
公开(公告)日:2024-01-16
申请号:US18086206
申请日:2022-12-21
Applicant: KIOXIA CORPORATION
Inventor: Noboru Okamoto , Toshikatsu Hida
CPC classification number: G06F11/1068 , G11C16/0483 , G11C16/20 , G11C16/26
Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.
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公开(公告)号:US11733888B2
公开(公告)日:2023-08-22
申请号:US17028087
申请日:2020-09-22
Applicant: Kioxia Corporation
Inventor: Shunichi Igahara , Toshikatsu Hida , Riki Suzuki , Takehiko Amaki , Suguru Nishikawa , Yoshihisa Kojima
CPC classification number: G06F3/0634 , G06F3/061 , G06F3/0604 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F12/0253 , G06F12/10 , G06F2212/1044 , G06F2212/657
Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.
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