公开(公告)号：US20150318262A1

公开(公告)日：2015-11-05

申请号：US14324136

申请日：2014-07-04

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Dong Wook Kim ,  Jae Sik Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/171 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/18161 ,  H05K3/4688 ,  H01L2924/014

Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first wafer level die), and a second die (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer, a first set of interconnects located in the first inorganic dielectric layer, a second dielectric layer different from the first inorganic dielectric layer, and a set of redistribution metal layers in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects.

Abstract translation: 一些新颖的特征涉及集成器件（例如，集成封装），其包括用于集成器件的基底部分，第一管芯（例如，第一晶片级管芯）和第二管芯（例如，第二晶片级管芯）。 基部包括第一无机电介质层，位于第一无机电介质层中的第一组互连，不同于第一无机介电层的第二电介质层和第二介电层中的一组再分布金属层。 第一管芯耦合到基部的第一表面。 第二管芯耦合到基部的第一表面，第二管芯通过第一组互连件电耦合到第一管芯。

公开(公告)号：US10049977B2

公开(公告)日：2018-08-14

申请号：US14450201

申请日：2014-08-01

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/495 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538

Abstract: A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure.

公开(公告)号：US09881859B2

公开(公告)日：2018-01-30

申请号：US14273882

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Shiqun Gu ,  Ratibor Radojcic

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/522 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/528 ,  H01L21/311 ,  H05K1/09 ,  H05K1/11 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/31127 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/20648 ,  H01L2924/3511 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09563 ,  H01L2924/014 ,  H01L2224/81

Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

公开(公告)号：US09799628B2

公开(公告)日：2017-10-24

申请号：US15043484

申请日：2016-02-12

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Hong Bok We ,  Jae Sik Lee ,  Shiqun Gu

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1146 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14151 ,  H01L2224/14155 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1624 ,  H01L2224/171 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/81 ,  H01L21/76898

Abstract: Some examples of the disclosure may include a package on package integrated package configuration including a first die located above the substrate in a first plane, a second die located above the first die in a second plane with a portion extending past the first die, a third die located above the first die in the second plane with a portion extending past the first die, a fourth die located above the second die and the third die in a third plane with a portion extending past the second die and the third die, and a fifth die located above the second die and the third die in the third plane with a portion extending past the second die and the third die.

公开(公告)号：US09633950B1

公开(公告)日：2017-04-25

申请号：US15040881

申请日：2016-02-10

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Jae Sik Lee ,  Dong Wook Kim

IPC: H01L23/49 ,  H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/5387 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49833 ,  H01L25/0652 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/1815

Abstract: Some features pertain to an integrated device that includes a first integrated circuit (IC) package, a flexible connector and a second integrated circuit (IC) package. The first integrated circuit (IC) package includes a first die, a plurality of first interconnects, and a first dielectric layer encapsulating the first die. The flexible connector is coupled to the first integrated circuit (IC) package. The flexible connector includes the first dielectric layer, and an interconnect. The second integrated circuit (IC) package is coupled to the flexible connector. The second integrated circuit (IC) package includes the first dielectric layer, and a plurality of second interconnects. The first integrated circuit (IC) package, the second integrated circuit (IC) package, and the flexible connector are coupled together through at least a portion (e.g., contiguous portion) of the first dielectric layer. In some implementations, the flexible connector comprises a dummy metal layer.

公开(公告)号：US09595494B2

公开(公告)日：2017-03-14

申请号：US14844185

申请日：2015-09-03

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/3157 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/19 ,  H01L24/25 ,  H01L24/27 ,  H01L24/33 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/19 ,  H01L2224/2205 ,  H01L2224/221 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: A semiconductor package according to some examples of the disclosure may include a substrate having a bridge embedded in the substrate, a first and second die coupled to the substrate, and a plurality of electrically conductive bridge interconnects in the substrate coupling the bridge to the first and second die. The plurality of electrically conductive bridge interconnects may have a first bridge contact layer directly coupled to the bridge, a first solder layer on the first bridge contact layer, a second bridge contact layer on the first solder layer, a second solder layer on the second bridge contact layer, and a die contact directly coupled to one of the first and second die where the plurality of electrically conductive bridge interconnects are embedded in the substrate.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括具有嵌入在衬底中的桥的衬底，耦合到衬底的第一和第二裸片以及耦合到第一和第二衬底的衬底中的多个导电桥互连 第二次死亡 多个导电桥互连可以具有直接耦合到桥的第一桥接触层，第一桥接触层上的第一焊料层，第一焊料层上的第二桥接触层，第二桥上的第二焊料层 接触层和直接耦合到所述第一和第二管芯中的一个的管芯接触，其中所述多个导电桥互连件嵌入在所述衬底中。

公开(公告)号：US09583462B2

公开(公告)日：2017-02-28

申请号：US14689011

申请日：2015-04-16

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim

IPC: H01L21/02 ,  H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2924/0002 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A semiconductor device may include a first semiconductor die. A passivation layer supports the first semiconductor die. The passivation layer may include a first via having a barrier layer and a first redistribution layer (RDL) conductive interconnect coupled to the first via through the barrier layer. The first via may couple the first semiconductor die to the first RDL conductive interconnect.

Abstract translation: 半导体器件可以包括第一半导体管芯。 钝化层支撑第一半导体管芯。 钝化层可以包括具有阻挡层的第一通孔和通过阻挡层耦合到第一通孔的第一再分布层（RDL）导电互连。 第一通孔可以将第一半导体管芯耦合到第一RDL导电互连。

公开(公告)号：US20160379959A1

公开(公告)日：2016-12-29

申请号：US15261731

申请日：2016-09-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Jae Sik Lee ,  Dong Wook Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32137 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/381 ,  H01L2924/00014

Abstract: An integrated circuit (IC) package structure may include a substrate. The substrate may include a semiconductor bridge having a first surface directly on a surface of the substrate that faces a first semiconductor die and a second semiconductor die. The semiconductor bridge may be disposed within a cavity extending through a photo-sensitive layer on the surface of the substrate. The semiconductor bridge may have an exposed, second surface substantially flush with the photo-sensitive layer. The first semiconductor die and the second semiconductor die are supported by the substrate and coupled together through the semiconductor bridge.

公开(公告)号：US09443824B1

公开(公告)日：2016-09-13

申请号：US14673435

申请日：2015-03-30

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Jae Sik Lee ,  Dong Wook Kim

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32137 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/381 ,  H01L2924/00014

Abstract: An integrated circuit (IC) package structure may include a substrate. The substrate may include a semiconductor bridge having a first surface directly on a surface of the substrate that faces a first semiconductor die and a second semiconductor die. The semiconductor bridge may be disposed within a cavity extending through a photo-sensitive layer on the surface of the substrate. The semiconductor bridge may have an exposed, second surface substantially flush with the photo-sensitive layer. The first semiconductor die and the second semiconductor die are supported by the substrate and coupled together through the semiconductor bridge.

Abstract translation: 集成电路（IC）封装结构可以包括衬底。 衬底可以包括半导体电桥，其具有直接位于衬底的面向第一半导体管芯和第二半导体管芯的表面上的第一表面。 半导体桥可以设置在延伸穿过衬底表面上的光敏层的空腔内。 半导体桥可以具有基本上与光敏层齐平的暴露的第二表面。 第一半导体管芯和第二半导体管芯由衬底支撑并通过半导体桥耦合在一起。

公开(公告)号：US09355963B2

公开(公告)日：2016-05-31

申请号：US14498076

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Jae Sik Lee ,  Hong Bok We ,  Young Kyu Song ,  Chin-Kwan Kim ,  Kyu-Pyung Hwang ,  Shiqun Gu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括在一侧具有第一再分布层的基底，在与第一再分布层相反的一侧上附接到基部的第一和第二并排裸片，附接到主动侧的插入件 以提供第一和第二管芯之间的互连，从第一和第二管芯延伸到在与第一再分布层相对的封装的表面上的第二再分配层的多个管芯通孔，以及多个 在第一和第二再分配层之间延伸穿过包装的通孔。