公开(公告)号：US20250029933A1

公开(公告)日：2025-01-23

申请号：US18770072

申请日：2024-07-11

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA ,  Shuuichi KARIYAZAKI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

Abstract: The performance of an electronic device can be improved. The electronic device includes a wiring substrate, a semiconductor memory device disposed on the wiring substrate, and a semiconductor control device disposed on the wiring substrate. The wiring substrate includes a first fixed potential wiring and a second fixed potential wiring, and a plurality of signal wirings arranged between the first fixed potential wiring and the second fixed potential wiring. The plurality of signal wirings includes a first signal wiring adjacent to the first fixed potential wiring, a second signal wiring adjacent to the first signal wiring, and a third signal wiring adjacent to the second signal wiring. A first distance between the first signal wiring and the second signal wiring is smaller than a second distance between the second signal wiring and the third signal wiring.

公开(公告)号：US20230335512A1

公开(公告)日：2023-10-19

申请号：US17720689

申请日：2022-04-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shuuichi KARIYAZAKI ,  Ryuichi OIKAWA

IPC: H01L23/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01P3/08

CPC classification number: H01L23/66 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/16 ,  H01L23/49822 ,  H01L23/49838 ,  H01P3/08 ,  H01L2223/6627 ,  H01L2224/16157 ,  H01L2924/19031 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: The wiring board has a first region overlapping a first semiconductor device and a second region not overlapping each of the first semiconductor device and a second semiconductor device. A first signal wiring of the wiring board has a first portion in the first region and a second portion in the second region. In a thickness direction of the wiring board, the second portion is between two ground patterns to which a reference potential is supplied, while the first portion has a portion not positioned between two ground patterns to which a reference potential is supplied. The first portion has a first wide portion having a larger width than a width of the second portion.

公开(公告)号：US20230066512A1

公开(公告)日：2023-03-02

申请号：US17841196

申请日：2022-06-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita TSUCHIYA ,  Shuuichi KARIYAZAKI ,  Kazuhiro MITAMURA

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/66 ,  H01P3/08

Abstract: A wiring substrate includes: a first insulating layer; a ground plane formed on the first insulating layer; a second insulating layer formed on the first insulating layer such that the ground plane is covered with the second insulating layer; a first signal wiring formed on the second insulating layer; a third insulating layer formed on the second insulating layer such that the first signal wiring is covered with the third insulating layer; and a second signal wiring formed on the third insulating layer and electrically connected with the first signal wiring. The first signal wiring is arranged in a region overlapping with a portion of a heat radiating plate. The second signal wiring is not arranged in the region. The ground plane has an opening portion located at a position overlapping with the first signal wiring. The opening portion is formed so as to extend along the first signal wiring.

公开(公告)号：US20200294954A1

公开(公告)日：2020-09-17

申请号：US16817172

申请日：2020-03-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Wataru SHIROI ,  Shuuichi KARIYAZAKI

IPC: H01L23/00 ,  H01L23/31

Abstract: The electronic device includes first and second semiconductor components. And, the electronic device includes a sealing body for sealing the first semiconductor component (i.e., the logic chip). A plurality of through conductors electrically connected to the first semiconductor component and/or the second semiconductor component is formed in the sealing body. In plan view, the sealing body has a first region in which the first semiconductor component is located, a second region located on a periphery of a first surface of the sealing body, a third region located between the second region and the first region, and a fourth region located between the second region and the third region. The plurality of through conductors is arranged most in the second region. The number of the plurality of through conductors located in the third region is larger than the number of the plurality of through conductors located in the fourth region.

公开(公告)号：US20200168540A1

公开(公告)日：2020-05-28

申请号：US16653098

申请日：2019-10-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshitaka OKAYASU ,  Shuuichi KARIYAZAKI

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/16

Abstract: The lower surface of the wiring substrate includes a first region overlapping with the semiconductor chip mounted on the upper surface, and a second region surrounding the first region and not overlapping with the semiconductor chip. The first region includes a third region in which the plurality of external terminals is not arranged, and a fourth region surrounding the third region in which the plurality of external terminals is arranged. The plurality of external terminals includes a plurality of terminals arranged in the fourth region of the first region and a plurality of terminals arranged in the second region. The plurality of terminals includes a plurality of power supply terminals for supplying a power supply potential to the core circuit of the semiconductor chip, and a plurality of reference terminals for supplying a reference potential to the core circuit of the semiconductor chip.

公开(公告)号：US20180158771A1

公开(公告)日：2018-06-07

申请号：US15721784

申请日：2017-09-30

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko AKIBA ,  Shuuichi KARIYAZAKI

IPC: H01L23/528 ,  H01L23/15 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/4901 ,  H01L2224/494 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: It is intended to reduce the price of a semiconductor device and increase the reliability thereof. In an interposer, a plurality of wiring layers are disposed between uppermost-layer wiring and lowermost-layer wiring. For example, a third wiring layer is electrically coupled directly to a first wiring layer as the uppermost-layer wiring by a long via wire extending through insulating layers without intervention of a second wiring layer. For example, an upper-surface terminal made of the first wiring layer is electrically coupled directly to a via land made of the third wiring layer by the long via wire. Between the adjacent long via wires, three lead-out wires made of the second wiring layer can be placed. The number of the lead-out wires that can be placed between the adjacent long via wires is larger than the number of the lead-out wires that can be placed between the adjacent via lands.

公开(公告)号：US20170213776A1

公开(公告)日：2017-07-27

申请号：US15515465

申请日：2014-12-24

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA ,  Toshihiko OCHIAI ,  Shuuichi KARIYAZAKI ,  Yuji KAYASHIMA ,  Tsuyoshi KIDA

IPC: H01L23/14 ,  H01L25/065 ,  H01L23/66 ,  H01L23/498

CPC classification number: H01L23/147 ,  H01L23/00 ,  H01L23/32 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/66 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/18 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

公开(公告)号：US20170179050A1

公开(公告)日：2017-06-22

申请号：US15295094

申请日：2016-10-17

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI

IPC: H01L23/66 ,  H05K1/02 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/642 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/5383 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6661 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/30111 ,  H05K1/0231 ,  H05K1/181 ,  H05K2201/10378

Abstract: A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer.

公开(公告)号：US20160190049A1

公开(公告)日：2016-06-30

申请号：US15059948

申请日：2016-03-03

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI ,  Ryuichi OIKAWA

IPC: H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5225 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16057 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K1/0225 ,  H05K1/0253 ,  H05K2201/09336 ,  H05K2201/09681 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.

公开(公告)号：US20150061104A1

公开(公告)日：2015-03-05

申请号：US14447181

申请日：2014-07-30

Applicant: Renesas Electronics Corporation

Inventor： Satoshi TAKAHASHI ,  Shuuichi KARIYAZAKI

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/544 ,  H01L23/367

CPC classification number: H01L23/04 ,  H01L21/50 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/544 ,  H01L23/562 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/74 ,  H01L24/97 ,  H01L25/165 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0913 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0266 ,  H05K3/3442 ,  H05K3/3489 ,  H05K2201/066 ,  H05K2201/09781 ,  H05K2201/1056 ,  H05K2201/10636 ,  H05K2203/0169 ,  H05K2203/0173 ,  H05K2203/167 ,  H05K2203/168 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014

Abstract: An error is prevented from being generated at a mounting position of an electronic component on a wiring substrate. A first semiconductor chip has a main surface and a rear surface. The rear surface is an opposite surface of the main surface. The rear surface of the first semiconductor chip is an opposite surface of the main surface thereof. A wiring substrate is rectangular, and has a main surface and a rear surface. The first semiconductor chip is mounted on the main surface of the wiring substrate. A lid covers the main surface of the wiring substrate, and the first semiconductor chip. An electronic component is mounted on the rear surface of the wiring substrate. The main surface of the wiring substrate has uncovered regions that are not covered with the lid at at least two corners facing each other.

Abstract translation: 防止在布线基板上的电子部件的安装位置产生误差。 第一半导体芯片具有主表面和后表面。 后表面是主表面的相反表面。 第一半导体芯片的后表面是其主表面的相对表面。 布线基板是矩形的，并且具有主表面和后表面。 第一半导体芯片安装在布线基板的主表面上。 盖子覆盖布线基板的主表面和第一半导体芯片。 电子部件安装在布线基板的背面。 布线基板的主表面在至少两个彼此面对的角部处未被盖子覆盖的未覆盖区域。