公开(公告)号：US20130199441A1

公开(公告)日：2013-08-08

申请号：US13828585

申请日：2013-03-14

Applicant: SOITEC

Inventor： Chantal Arena ,  Ronald Thomas Bertram, JR. ,  Ed Lindow ,  Christiaan Werkhoven

IPC: C30B25/14

CPC classification number: C30B25/14 ,  C30B25/10 ,  C30B29/40

Abstract: The present invention provides improved gas injectors for use with CVD (chemical vapour deposition) systems that thermalize gases prior to injection into a CVD chamber. The provided injectors are configured to increase gas flow times through heated zones and include gas-conducting conduits that lengthen gas residency times in the heated zones. The provided injectors also have outlet ports sized, shaped, and arranged to inject gases in selected flow patterns. The invention also provides CVD systems using the provided thermalizing gas injectors. The present invention has particular application to high volume manufacturing of GaN substrates.

Abstract translation: 本发明提供了用于CVD（化学气相沉积）系统的改进的气体注入器，其在注入CVD腔室之前对气体进行热化。 所提供的喷射器构造成通过加热区增加气流时间，并且包括延长加热区中的气体驻留时间的导气导管。 所提供的注射器还具有尺寸，形状和布置成以选定的流动模式注入气体的出口端口。 本发明还提供了使用所提供的热化气体喷射器的CVD系统。 本发明特别适用于大量制造GaN衬底。

公开(公告)号：US20130104802A1

公开(公告)日：2013-05-02

申请号：US13680241

申请日：2012-11-19

Applicant: Soitec

Inventor： Chantal Arena ,  Christiaan Werkhoven

IPC: C30B25/10

CPC classification number: C30B25/10 ,  C23C16/303 ,  C23C16/4411 ,  C23C16/4412 ,  C23C16/45504 ,  C23C16/45593 ,  C30B25/14 ,  C30B29/406 ,  C30B35/00 ,  H01L21/0254 ,  H01L21/0262

Abstract: A system for epitaxial deposition of a Group III-V semiconductor material that includes gallium. The system includes sources of the reactants, one of which is a gaseous Group III precursor having one or more gaseous gallium precursors and another of which is a gaseous Group V component, a reaction chamber wherein the reactants combine to deposit Group III-V semiconductor material, and one or more heating structures for heating the gaseous Group III precursors prior to reacting to a temperature to decompose substantially all dimers, trimers or other molecular variations of such precursors into their monomer forms.

Abstract translation: 一种用于外延沉积包括镓的III-V族III族半导体材料的系统。 该系统包括反应物的源，其中之一是具有一种或多种气态镓前体的气态III族前体，另一种是气态V族组分，其中反应物结合沉积III-V族半导体材料 以及一个或多个加热结构，用于在反应温度之前加热气态III族前体，以将这些前体的基本上所有的二聚体，三聚体或其它分子变体分解为它们的单体形式。

公开(公告)号：US10014429B2

公开(公告)日：2018-07-03

申请号：US14749334

申请日：2015-06-24

Applicant: Soitec

Inventor： Fred Newman ,  Frank Reinhardt ,  Chantal Arena

IPC: H01L31/06 ,  H01L31/04 ,  H01L31/18 ,  H01L31/0687 ,  H01L31/0693 ,  H01L31/0304 ,  H01L31/043

CPC classification number: H01L31/0687 ,  H01L31/03042 ,  H01L31/03046 ,  H01L31/03048 ,  H01L31/043 ,  H01L31/0693 ,  H01L31/184 ,  H01L31/1844 ,  H01L31/1852 ,  H01L31/1892 ,  Y02E10/544

Abstract: A method of fabricating a semiconductor structure includes the formation of a first bonding layer at least substantially comprised of a first III-V material on a major surface of a first element, and formation of a second bonding layer at least substantially comprised of a second III-V material on a major surface of a second element. The first bonding layer and the second bonding layer are disposed between the first element and the second element, and the first element and the second element are attached to one another at a bonding interface disposed between the first bonding layer and the second bonding layer. Semiconductor structures are fabricated using such methods.

公开(公告)号：US09978905B2

公开(公告)日：2018-05-22

申请号：US15141472

申请日：2016-04-28

Applicant: Soitec

Inventor： Jean-Philippe Debray ,  Chantal Arena ,  Heather McFavilen

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L33/14 ,  H01L21/02

CPC classification number: H01L33/06 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L33/007 ,  H01L33/12 ,  H01L33/145 ,  H01L33/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1−wN, and at least one barrier layer comprising InbGa1−bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1−wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1−bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light-emitting device, such as an LED. Luminary devices include such LEDs.

公开(公告)号：US09634182B2

公开(公告)日：2017-04-25

申请号：US14991100

申请日：2016-01-08

Applicant: Soitec

Inventor： Jean-Philippe Debray ,  Chantal Arena ,  Heather McFavilen ,  Ding Ding ,  Li Huang

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L33/14 ,  H01L33/04 ,  H01L33/16

CPC classification number: H01L33/06 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/04 ,  H01L33/12 ,  H01L33/145 ,  H01L33/16 ,  H01L33/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

公开(公告)号：US09324911B2

公开(公告)日：2016-04-26

申请号：US13720284

申请日：2012-12-19

Applicant: Soitec

Inventor： Chantal Arena ,  Robin Scott ,  Claudio Canizares

IPC: H01L33/32 ,  H01L21/02 ,  H01L31/0687 ,  H01L27/15 ,  H01L31/0304 ,  H01L31/18 ,  H01S5/323 ,  H01L33/00 ,  H01L33/08

CPC classification number: H01L33/32 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02664 ,  H01L27/153 ,  H01L31/03048 ,  H01L31/0687 ,  H01L31/1848 ,  H01L33/0062 ,  H01L33/08 ,  H01S5/32341 ,  H01S5/32358 ,  Y02E10/544

Abstract: Dilute nitride III-V semiconductor materials may be formed by substituting As atoms for some N atoms within a previously formed nitride material to transform at least a portion of the previously formed nitride material into a dilute nitride III-V semiconductor material that includes arsenic. Such methods may be employed in the fabrication of photoactive devices, such as photovoltaic cells and photoemitters. The methods may be carried out within a deposition chamber, such as a metalorganic chemical vapor deposition (MOCVD) or a hydride vapor phase epitaxy (HVPE) chamber.

Abstract translation: 稀氮化物III-V半导体材料可以通过用先前形成的氮化物材料中的一些N原子取代As原子将至少一部分先前形成的氮化物材料转化成包括砷的稀氮化物III-V半导体材料来形成。 这种方法可以用于制造光电器件，例如光伏电池和光电放电器。 该方法可以在沉积室内进行，例如金属有机化学气相沉积（MOCVD）或氢化物气相外延（HVPE）室。

公开(公告)号：US09246057B2

公开(公告)日：2016-01-26

申请号：US14211590

申请日：2014-03-14

Applicant: Soitec

Inventor： Jean-Philippe Debray ,  Chantal Arena ,  Heather McFavilen ,  Ding Ding ,  Li Huang

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  H01L33/04 ,  H01L33/16

CPC classification number: H01L33/06 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/04 ,  H01L33/12 ,  H01L33/145 ,  H01L33/16 ,  H01L33/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

Abstract translation: 半导体结构包括多层InGaN之间的有源区。 有源区可以至少基本上由InGaN组成。 多层InGaN包括至少一个包含InwGa1-wN的阱层和至少一个包含接近至少一个阱层的InbGa1-bN的势垒层。 在一些实施例中，阱层的InwGa1-wN中的w的值在一些实施例中可以大于或等于约0.10且小于或等于约0.40，并且在InbGa1-bN中的b的值在 至少一个阻挡层可以大于或等于约0.01且小于或等于约0.10。 形成半导体结构的方法包括生长这样的InGaN层以形成诸如LED的发光器件的有源区。 照明装置包括这样的LED。

公开(公告)号：US20150340430A1

公开(公告)日：2015-11-26

申请号：US14817464

申请日：2015-08-04

Applicant: Soitec

Inventor： Christiaan J. Werkhoven ,  Chantal Arena

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/26 ,  H01L29/20

CPC classification number: H01L21/2654 ,  H01L21/0242 ,  H01L21/02425 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02634 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/6835 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/0079 ,  H01L33/647 ,  H01L2221/68318 ,  H01L2221/68363

Abstract: Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments.

Abstract translation: 实施例涉及形成半导体结构的半导体结构和方法。 半导体结构包括具有与在衬底层上形成的一层或多层半导体材料的CTE紧密匹配的CTE的衬底层。 在一些实施例中，衬底层可以包括包括两个或更多个元件的复合衬底材料。 在一些实施例中，基底层可以包括金属材料和/或陶瓷材料。

公开(公告)号：US09012919B2

公开(公告)日：2015-04-21

申请号：US13738406

申请日：2013-01-10

Applicant: SOITEC

Inventor： Ed Lindow ,  Chantal Arena ,  Ronald Bertram ,  Ranjan Datta ,  Subhash Mahajan

IPC: H01L29/20 ,  H01L21/02

CPC classification number: H01L29/2003 ,  H01L21/0237 ,  H01L21/02455 ,  H01L21/02458 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02617 ,  H01L21/0262

Abstract: Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.

Abstract translation: 本发明的实施例涉及制造半导体结构的方法以及通过这些方法制造的半导体结构。 在一些实施例中，该方法可用于制造诸如InGaN的III-V材料的半导体结构。 通过使用不同的生长条件生长子层来制造半导体层，以改善所得层的均匀性，改善所得层的表面粗糙度和/或使层能够生长到增加的厚度而不发生 的应变松弛。

公开(公告)号：US20150027519A1

公开(公告)日：2015-01-29

申请号：US14387518

申请日：2013-03-13

Applicant: Soitec

Inventor： Bruno Ghyselen ,  Chantal Arena ,  Frank Dimroth ,  Andreas W. Bett

IPC: H01L31/0725 ,  H01L31/18

CPC classification number: H01L31/0725 ,  C30B29/06 ,  C30B33/06 ,  H01L31/03046 ,  H01L31/0687 ,  H01L31/1844 ,  H01L31/1852 ,  Y02E10/544 ,  Y02P70/521

Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first substrate, providing a second substrate having a lower surface and an upper surface, forming at least one first solar cell layer on the first substrate to obtain a first wafer structure, forming at least one second solar cell layer on the upper surface of the second substrate to obtain a second wafer structure, and bonding the first wafer structure to the second wafer structure, wherein the at least one first solar cell layer is bonded to the lower surface of the second substrate and removing the first substrate.

Abstract translation: 本发明涉及一种用于制造多结太阳能电池器件的方法，包括以下步骤：提供第一衬底，提供具有下表面和上表面的第二衬底，在第一衬底上形成至少一个第一太阳能电池层 以获得第一晶片结构，在所述第二衬底的上表面上形成至少一个第二太阳能电池层以获得第二晶片结构，并将所述第一晶片结构接合到所述第二晶片结构，其中所述至少一个第一太阳能电池 将单元层结合到第二基板的下表面并除去第一基板。