公开(公告)号：US09076891B2

公开(公告)日：2015-07-07

申请号：US13754513

申请日：2013-01-30

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Juan Herbsommer

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/49 ,  H01L23/28 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49883 ,  H01L24/06 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05078 ,  H01L2224/05573 ,  H01L2224/0603 ,  H01L2224/29026 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83851 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/00015

Abstract: An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.

Abstract translation: 集成电路（“IC”）组件包括其顶表面上具有金属化层的IC管芯。 多个引线在其第一端部处接合到金属化层。 导电层附接到金属化层并覆盖引线的第一端。

公开(公告)号：US20240224415A1

公开(公告)日：2024-07-04

申请号：US18603099

申请日：2024-03-12

Applicant: Texas Instruments Incorporated

Inventor： Tianyi Luo ,  Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Bernardo Gallegos

IPC: H05K1/02 ,  H01L21/50 ,  H01L21/60 ,  H01L23/00 ,  H01L23/538

CPC classification number: H05K1/0271 ,  H01L21/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14 ,  H01L2021/60097 ,  H01L2224/16225

Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.

公开(公告)号：US11784114B2

公开(公告)日：2023-10-10

申请号：US17334491

申请日：2021-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria Noquil ,  Makarand Ramkrishna Kulkarni ,  Osvaldo Jorge Lopez ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Liang Wan

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49844 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16238

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

公开(公告)号：US20190385992A1

公开(公告)日：2019-12-19

申请号：US16546475

申请日：2019-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L25/18 ,  H01L23/00 ,  H01L21/50 ,  H01L23/14 ,  H01L23/13 ,  H01L23/06 ,  H01L23/053 ,  H01L29/06 ,  H01L25/00 ,  H01L31/02 ,  H01L31/18 ,  H01L27/088 ,  H01L27/082 ,  H01L31/0216 ,  H01L31/042 ,  H01L31/028

Abstract: A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US10438936B2

公开(公告)日：2019-10-08

申请号：US15820246

申请日：2017-11-21

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/028 ,  H01L31/042 ,  H01L31/0216 ,  H01L27/082 ,  H01L27/088 ,  H01L31/18 ,  H01L31/02 ,  H01L25/00 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/14 ,  H01L21/50 ,  H01L23/00 ,  H01L25/18 ,  H01L29/06 ,  H01L23/498

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US20180331083A1

公开(公告)日：2018-11-15

申请号：US16027031

申请日：2018-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez ,  Haian Lin

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H02M3/155 ,  H01L21/768 ,  H02M3/158

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73251 ,  H01L2224/80001 ,  H01L2224/9222 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/1425 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H02M3/155 ,  H02M3/158 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.

公开(公告)号：US10050025B2

公开(公告)日：2018-08-14

申请号：US15019275

申请日：2016-02-09

Applicant: Texas Instruments Incorporated

Inventor： Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez ,  Haian Lin

IPC: H01L23/495 ,  H01L25/16 ,  H01L23/00 ,  H01L25/07 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H02M3/155 ,  H01L21/768 ,  H02M3/158

Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.

公开(公告)号：US09935041B1

公开(公告)日：2018-04-03

申请号：US15480999

申请日：2017-04-06

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil

IPC: H01L23/495 ,  H01L23/525 ,  H01L21/48 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L23/49575 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/38 ,  H01L24/40 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/40257 ,  H01L2224/83191 ,  H01L2924/1304 ,  H01L2924/14

Abstract: A clip tape includes connected clip sets; each includes a first clip and a second clip oriented in a same direction, connected by a connector bar. A first multi-chip module and a second multi-chip module are formed by providing a lead frame array containing lead frame units, and providing a clip tape containing connected clip sets. A connected clip set is separated from the clip tape as a unit and placed on the lead frame array; the first clip in the first multi-chip module, and the second clip in the second multi-chip module. The connector bar remains attached during a heating operation, and is severed by a singulation process. A multi-chip module includes a lead frame unit, a semiconductor device, and a clip of a connected clip set attached to the semiconductor device. A connector bar extends from the clip to an external surface of the multi-chip module.

公开(公告)号：US20170194306A1

公开(公告)日：2017-07-06

申请号：US15465455

申请日：2017-03-21

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/0216 ,  H01L31/028 ,  H01L25/00 ,  H01L31/18 ,  H01L27/082 ,  H01L27/088 ,  H01L31/02 ,  H01L31/042

CPC classification number: H01L25/167 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/088 ,  H01L29/0657 ,  H01L31/02008 ,  H01L31/02168 ,  H01L31/028 ,  H01L31/042 ,  H01L31/1804 ,  H01L31/1868 ,  H01L2224/83851 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US09653388B2

公开(公告)日：2017-05-16

申请号：US14938422

申请日：2015-11-11

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/00 ,  H01L21/50 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: A electronic multi-output device having a substrate including a pad and pins. A composite first chip has a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface. Patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. The second terminals are connected by discrete first and second metal clips to respective substrate pins. A composite second chip has a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to be vertically attached with its first terminals to the first and second clips, respectively. The third terminals are connected by discrete clips to respective substrate pins. The common second terminal is connected by a common clip to a substrate pin.