公开(公告)号：US20170125574A1

公开(公告)日：2017-05-04

申请号：US15344377

申请日：2016-11-04

Applicant: The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Jeonghee Kim ,  Chirag Gupta ,  Stacia Keller ,  Silvia H. Chan ,  Umesh K. Mishra

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/861

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

公开(公告)号：US20160163846A1

公开(公告)日：2016-06-09

申请号：US15009509

申请日：2016-01-28

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Xiang Liu ,  Umesh K. Mishra ,  Stacia Keller ,  Jeonghee Kim ,  Matthew Laurent ,  Jing Lu ,  Ramya Yeluri ,  Silvia H. Chan

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  C30B25/02 ,  C30B29/20 ,  C30B29/406 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.

公开(公告)号：US09231376B2

公开(公告)日：2016-01-05

申请号：US14229674

申请日：2014-03-28

Applicant: The Regents of the University of California

Inventor： Robert M. Farrell, Jr. ,  Troy J. Baker ,  Arpan Chakraborty ,  Benjamin A. Haskell ,  P. Morgan Pattison ,  Rajat Sharma ,  Umesh K. Mishra ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

IPC: H01L33/30 ,  H01S5/343 ,  B82Y20/00 ,  C30B23/02 ,  C30B25/18 ,  C30B29/40 ,  H01L21/02 ,  H01L33/00 ,  H01S5/042 ,  H01S5/22 ,  H01S5/32

CPC classification number: H01L33/16 ,  B82Y20/00 ,  C30B23/025 ,  C30B25/18 ,  C30B29/403 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L33/0004 ,  H01L33/0062 ,  H01L33/007 ,  H01L33/02 ,  H01S5/0422 ,  H01S5/2201 ,  H01S5/3202 ,  H01S5/34333 ,  H01S2304/04

Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

Abstract translation: 一种用于生长和制造半极性（Ga，Al，In，B）N薄膜，异质结构和器件的方法，包括鉴定特定器件应用的所需材料性质，基于所需材料性质选择半极性生长取向，选择 用于生长选择的半极性生长取向的合适底物，在衬底上生长平面半极性（Ga，Al，In，B）N模板或成核层，以及生长半极（Ga，Al，In，B）N薄膜 ，平面半极性（Ga，Al，In，B）N模板或成核层上的异质结构或器件。 该方法导致大面积的半极性（Ga，Al，In，B）N薄膜，异质结构和器件平行于衬底表面。

公开(公告)号：US20150200286A1

公开(公告)日：2015-07-16

申请号：US14597989

申请日：2015-01-15

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Xiang Liu ,  Umesh K. Mishra ,  Stacia Keller ,  Jeonghee Kim ,  Matthew Laurent ,  Jing Lu ,  Ramya Yeluri ,  Silvia H. Chan

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7787 ,  C30B25/02 ,  C30B29/20 ,  C30B29/406 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.

Abstract translation: 一种制造III族氮化物半导体器件的方法，包括在氧化物生长和III族氮化物半导体的生长之间不暴露于空气中，依次生长III族氮化物半导体和氧化物以形成氧化物/ III族氮化物界面 。

公开(公告)号：US20150076533A1

公开(公告)日：2015-03-19

申请号：US14553625

申请日：2014-11-25

Applicant: The Regents of the University of California

Inventor： Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

IPC: H01L27/15 ,  H01L33/62

CPC classification number: H01L25/0753 ,  F21K9/00 ,  H01L27/156 ,  H01L33/08 ,  H01L33/14 ,  H01L33/20 ,  H01L33/38 ,  H01L33/385 ,  H01L33/42 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00

Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistance with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

Abstract translation: 本发明公开了排列成阵列的多个叉指像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。 每个像素是具有尺寸l的边的正方形。 通过增加像素的有源区域的周长来使串联电阻最小化。 串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

公开(公告)号：US08922110B2

公开(公告)日：2014-12-30

申请号：US14311071

申请日：2014-06-20

Applicant: The Regents of the University of California

Inventor： Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

IPC: H01J1/62 ,  H01L33/14 ,  H01L33/08

CPC classification number: H01L25/0753 ,  F21K9/00 ,  H01L27/156 ,  H01L33/08 ,  H01L33/14 ,  H01L33/20 ,  H01L33/38 ,  H01L33/385 ,  H01L33/42 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00

Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

Abstract translation: 本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。 每个像素是具有尺寸l的边的正方形。 通过增加像素的有源区域的周长来使串联电阻最小化。 串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

公开(公告)号：US20140367698A1

公开(公告)日：2014-12-18

申请号：US14466420

申请日：2014-08-22

Applicant: The Regents of the University of California

Inventor： Hugues Marchand ,  Brendan J. Moran ,  Umesh K. Mishra ,  James S. Speck

IPC: H01L23/00 ,  H01L29/205 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L23/562 ,  C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/0025 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.

Abstract translation: 公开了控制沉积在硅和碳化硅衬底上的GaN膜中的应力控制方法和由其制备的膜。 典型的方法包括提供衬底并在衬底上沉积梯度的氮化镓层，其具有基本上连续等级的从初始组成到由生长室中的至少一种前体的供应形成的最终组成的变化的组成，而不会中断 在供应。 典型的半导体膜包括沉积在衬底上的衬底和梯度的氮化镓层，其具有从初始组成到最终组成的基本连续等级的变化的组成，其由在生长室中供应至少一种前体而形成，而不会中断 在供应。

公开(公告)号：US20140299900A1

公开(公告)日：2014-10-09

申请号：US14311071

申请日：2014-06-20

Applicant: The Regents of the University of California

Inventor： Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

IPC: H01L33/08 ,  H01L33/14

CPC classification number: H01L25/0753 ,  F21K9/00 ,  H01L27/156 ,  H01L33/08 ,  H01L33/14 ,  H01L33/20 ,  H01L33/38 ,  H01L33/385 ,  H01L33/42 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00

Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking Each pixel is a square with sides of dimension 1. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

Abstract translation: 本发明公开了一种排列成阵列的多个交错像素，其具有非常低的串联电阻，并具有改进的电流扩散和改进的散热。每个像素是具有尺寸1侧面的正方形。通过增加周长来使串联电阻最小化 的像素的活动区域。 串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

公开(公告)号：US12230678B2

公开(公告)日：2025-02-18

申请号：US17291842

申请日：2019-11-07

Applicant: The Regents of the University of California

Inventor： Umesh K. Mishra ,  Stacia Keller ,  Elaheh Ahmadi ,  Chirag Gupta ,  Yusuke Tsukada

IPC: H01L29/20 ,  H01L27/092 ,  H01L29/205 ,  H01L29/737 ,  H01L29/778 ,  H01L29/78 ,  H01L33/32

Abstract: The disclosure describes the use of strain to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition

公开(公告)号：US11594625B2

公开(公告)日：2023-02-28

申请号：US16802388

申请日：2020-02-26

Applicant: The Regents of the University of California

Inventor： Matthew Guidry ,  Stacia Keller ,  Umesh K. Mishra ,  Brian Romanczyk ,  Xun Zheng

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.