公开(公告)号：US09299660B2

公开(公告)日：2016-03-29

申请号：US13977473

申请日：2011-11-14

申请人： Weng Hong Teh ,  Shan Zhong

发明人： Weng Hong Teh ,  Shan Zhong

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L21/82 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/10 ,  H01L25/18

CPC分类号： H01L23/5384 ,  H01L21/82 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0331 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A process of bumping a die backside includes opening a recess in a die backside film (DBF) to expose a through-silicon via (TSV) contact in a die, followed by filling the recess with a conductive material that contacts the TSV contact. Added solder is coupled to the conductive material at a level of the DBF. A subsequent die is coupled to the first die at the added solder to form an electrical coupling consisting of the TSV contact, the conductive material, and the added solder, an electrical bump coupled to the subsequent die. Apparatus and computer systems are assembled using the process.

摘要翻译： 冲模模具背面的过程包括在模具背面薄膜（DBF）中打开凹部以暴露模具中的硅 - 硅通孔（TSV）接触，然后用与TSV触点接触的导电材料填充凹部。 添加的焊料在DBF的水平处耦合到导电材料。 随后的管芯在添加的焊料处耦合到第一管芯，以形成由TSV接触，导电材料和添加的焊料组成的电耦合，耦合到后续管芯的电凸点。 装置和计算机系统使用该过程组装。

公开(公告)号：US20140169800A1

公开(公告)日：2014-06-19

申请号：US13717185

申请日：2012-12-17

申请人： Feras Eid ,  Johanna Swan ,  Weng Hong Teh

发明人： Feras Eid ,  Johanna Swan ,  Weng Hong Teh

IPC分类号： H04B10/40 ,  F21V21/00 ,  H01L33/00

CPC分类号： H01S5/02272 ,  H01L21/568 ,  H01L24/18 ,  H01L24/19 ,  H01L25/167 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2924/12042 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02288 ,  H01S5/02292 ,  H01S5/183 ,  H01S5/18305 ,  H01L2924/00

摘要： This disclosure relates generally to an electronic package that can include a die and a dielectric layer at least partially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the dielectric layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic package different from the first major surface.

摘要翻译： 本公开一般涉及一种电子封装，其可以包括至少部分地包封管芯的管芯和电介质层。 电互连可以电耦合到管芯并且至少部分地通过电介质层。 光发射器可以用电互连的第一个电耦合到管芯，并且被配置为从电子封装的第一主表面发射光。 焊料凸块可以用电互连的第二个电耦合到管芯，并且位于电子封装的不同于第一主表面的第二主表面上。

公开(公告)号：US09601421B2

公开(公告)日：2017-03-21

申请号：US13976356

申请日：2011-12-30

申请人： Weng Hong Teh ,  Deepak V. Kulkarni

发明人： Weng Hong Teh ,  Deepak V. Kulkarni

IPC分类号： H01L23/498 ,  H01L23/00 ,  H05K3/46 ,  H05K3/00

CPC分类号： H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/3511 ,  H05K3/0097 ,  H05K3/4682 ,  H05K2201/10674 ,  H01L2924/00

摘要： An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a primary core adjacent at least a pair of the lateral sidewalls of the die; and a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die. A method of forming a package and an apparatus including a computing device including a package are also disclosed.

公开(公告)号：US09520350B2

公开(公告)日：2016-12-13

申请号：US13801859

申请日：2013-03-13

申请人： Weng Hong Teh ,  Emile Davies-Venn ,  Ebrahim Andideh ,  Digvijay A. Raorane ,  Daniel N. Sobieski

发明人： Weng Hong Teh ,  Emile Davies-Venn ,  Ebrahim Andideh ,  Digvijay A. Raorane ,  Daniel N. Sobieski

IPC分类号： H01L23/498 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/49822 ,  H01L21/76807 ,  H01L21/7681 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/19 ,  H01L2221/1026 ,  H01L2224/12105 ,  H01L2924/18162

摘要： Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.

摘要翻译： 描述了具有超薄电介质层的无创积层（BBUL）半导体封装。 例如，一种装置包括具有多个外部导电凸块的集成电路的半导体管芯。 半导体封装容纳半导体管芯。 半导体封装包括设置在多个外部导电凸块上方的电介质层。 导电通孔设置在电介质层中并耦合到多个导电凸块之一。 导电线设置在电介质层上并耦合到导电通孔。

公开(公告)号：US09297824B2

公开(公告)日：2016-03-29

申请号：US13618003

申请日：2012-09-14

申请人： Qing Ma ,  Valluri Rao ,  Feras Eid ,  Kevin Lin ,  Weng Hong Teh ,  Johanna Swan ,  Robert Sankman

发明人： Qing Ma ,  Valluri Rao ,  Feras Eid ,  Kevin Lin ,  Weng Hong Teh ,  Johanna Swan ,  Robert Sankman

IPC分类号： G01P15/105 ,  G01P15/08 ,  G01P15/097 ,  G01P15/18

CPC分类号： G01P15/097 ,  G01P15/105 ,  G01P15/18

摘要： An accelerometer includes a mass, suspended by a beam, and associated conductive paths. Each conductive path is subjected to a magnetic field, such that, when a time varying signal is applied to the conductive paths, a characteristic resonant frequency is produced, and when the mass experiences an acceleration, a respective change in the resonant frequency is produced that may be interpreted as acceleration data. Embodiments include methods of manufacturing an accelerometer and systems and devices incorporating the accelerometer.

摘要翻译： 加速度计包括由梁悬挂的质量块和相关联的导电路径。 每个导电路径受到磁场的影响，使得当对导电路径施加时变信号时，产生特性谐振频率，并且当质量经历加速度时，产生谐振频率的相应变化， 可以解释为加速度数据。 实施例包括制造加速度计的方法和结合有加速度计的系统和装置。

公开(公告)号：US20160076961A1

公开(公告)日：2016-03-17

申请号：US14951422

申请日：2015-11-24

申请人： Kevin L. Lin ,  Qing Ma ,  Feras Eid ,  Johanna Swan ,  Weng Hong Teh

发明人： Kevin L. Lin ,  Qing Ma ,  Feras Eid ,  Johanna Swan ,  Weng Hong Teh

IPC分类号： G01L9/00 ,  B81B7/00

CPC分类号： G01L9/0042 ,  B81B7/0058 ,  B81B7/0077 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/00246 ,  G01L9/0047 ,  G01L9/007 ,  G01L9/0073 ,  H01L24/19 ,  H01L29/84 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/1461 ,  H01L2924/18162

摘要： A semiconductor package having an air pressure sensor and methods to form a semiconductor package having an air pressure sensor are described. For example, a semiconductor package includes a plurality of build-up layers. A cavity is disposed in one or more of the build-up layers. An air pressure sensor is disposed in the plurality of build-up layers and includes the cavity and an electrode disposed above the cavity. Also described are various approaches to fabricating a semiconductor package having a hermetically sealed region.

摘要翻译： 描述了具有空气压力传感器的半导体封装和形成具有气压传感器的半导体封装的方法。 例如，半导体封装包括多个堆积层。 空腔设置在一个或多个堆积层中。 空气压力传感器设置在多个积聚层中，并且包括空腔和设置在空腔上方的电极。 还描述了制造具有气密密封区域的半导体封装的各种方法。

公开(公告)号：US09200973B2

公开(公告)日：2015-12-01

申请号：US13536210

申请日：2012-06-28

申请人： Kevin L. Lin ,  Qing Ma ,  Feras Eid ,  Johanna Swan ,  Weng Hong Teh

发明人： Kevin L. Lin ,  Qing Ma ,  Feras Eid ,  Johanna Swan ,  Weng Hong Teh

IPC分类号： G01L9/16 ,  G01L9/00 ,  B81B7/00 ,  B81C1/00 ,  H01L29/84

CPC分类号： G01L9/0042 ,  B81B7/0058 ,  B81B7/0077 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/00246 ,  G01L9/0047 ,  G01L9/007 ,  G01L9/0073 ,  H01L24/19 ,  H01L29/84 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/1461 ,  H01L2924/18162

摘要： A semiconductor package having an air pressure sensor and methods to form a semiconductor package having an air pressure sensor are described. For example, a semiconductor package includes a plurality of build-up layers. A cavity is disposed in one or more of the build-up layers. An air pressure sensor is disposed in the plurality of build-up layers and includes the cavity and an electrode disposed above the cavity. Also described are various approaches to fabricating a semiconductor package having a hermetically sealed region.

摘要翻译： 描述了具有空气压力传感器的半导体封装和形成具有气压传感器的半导体封装的方法。 例如，半导体封装包括多个堆积层。 空腔设置在一个或多个堆积层中。 空气压力传感器设置在多个积聚层中，并且包括空腔和设置在空腔上方的电极。 还描述了制造具有气密密封区域的半导体封装的各种方法。

公开(公告)号：US09162867B2

公开(公告)日：2015-10-20

申请号：US13977122

申请日：2011-12-13

申请人： Weng Hong Teh ,  Robert Bob L. Sankman

发明人： Weng Hong Teh ,  Robert Bob L. Sankman

IPC分类号： H01L25/065 ,  B81B3/00 ,  B81C1/00 ,  G01P15/135 ,  H01L23/48 ,  H01H1/00 ,  H01L23/13 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC分类号： B81B3/0021 ,  B81B2201/014 ,  B81B2201/0235 ,  B81B2203/0118 ,  B81C1/0015 ,  G01P15/135 ,  H01H1/0036 ,  H01H1/0094 ,  H01L21/563 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/05 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/831 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A process of forming a through-silicon via (TSV) in a die includes forming a movable member in the TSV that can be actuated or that can be a sensor. Action of the movable member in the TSV can result in a logic word being sent from the TSV die to a subsequent die. The TSV die may be embedded in a substrate. The TSV die may also be coupled to a subsequent die.

摘要翻译： 在模具中形成贯通硅通孔（TSV）的工艺包括在可被致动的TSV中形成可移动部件，或者可以是传感器。 可移动部件在TSV中的动作可导致将逻辑字从TSV管芯发送到随后的管芯。 TSV管芯可以嵌入衬底中。 TSV管芯也可以连接到随后的管芯。

公开(公告)号：US20150084139A1

公开(公告)日：2015-03-26

申请号：US14129541

申请日：2013-09-25

申请人： Weng Hong Teh ,  Tarek A. Ibrahim ,  Sarah K. Haney ,  Daniel N. Sobieski ,  Parshuram B. Zantye ,  Chad E. Mair ,  Telesphor Kamgaing

发明人： Weng Hong Teh ,  Tarek A. Ibrahim ,  Sarah K. Haney ,  Daniel N. Sobieski ,  Parshuram B. Zantye ,  Chad E. Mair ,  Telesphor Kamgaing

IPC分类号： B81B3/00 ,  B81C1/00

CPC分类号： B81C1/00246 ,  B81B2201/0271 ,  B81C1/00261 ,  B81C1/00277 ,  H01L21/568 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2924/01079

摘要： Techniques and mechanisms for providing precisely fabricated structures of a semiconductor package. In an embodiment, a build-up carrier of the semiconductor package includes a layer of porous dielectric material. Seed copper and plated copper is disposed on the layer of porous dielectric material. Subsequent etching is performed to remove copper adjacent to the layer of porous dielectric material, forming a gap separating a suspended portion of a MEMS structure from the layer of porous dielectric material. In another embodiment, the semiconductor package includes a copper structure disposed between portions of an insulating layer or portions of a layer of silicon nitride material. The layer of silicon nitride material couples the insulating layer to another insulating layer. One or both of the insulating layers are each protected from desmear processing with a respective release layer structure.

摘要翻译： 用于提供半导体封装的精确制造结构的技术和机构。 在一个实施例中，半导体封装的积聚载体包括多孔介电材料层。 种子铜和电镀铜设置在多孔电介质材料层上。 进行随后的蚀刻以去除邻近多孔介电材料层的铜，形成将MEMS结构的悬置部分与多孔介电材料层分开的间隙。 在另一个实施例中，半导体封装包括设置在绝缘层的一部分之间或者氮化硅材料层的一部分的铜结构。 氮化硅材料层将绝缘层耦合到另一绝缘层。 每个绝缘层中的一个或两个保护层不受去离子处理的剥离层结构的剥离。

公开(公告)号：US20140217599A1

公开(公告)日：2014-08-07

申请号：US13976356

申请日：2011-12-30

申请人： Weng Hong Teh ,  Deepak V. Kulkarni

发明人： Weng Hong Teh ,  Deepak V. Kulkarni

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/3511 ,  H05K3/0097 ,  H05K3/4682 ,  H05K2201/10674 ,  H01L2924/00

摘要： An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a primary core adjacent at least a pair of the lateral sidewalls of the die; and a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die. A method of forming a package and an apparatus including a computing device including a package are also disclosed.

摘要翻译： 一种包括模具的装置，包括第一侧和相对的第二侧，包括具有限定模具的厚度的接触点和侧壁的装置侧; 与芯片的至少一对侧壁相邻的主芯; 以及耦合到所述管芯的第二侧的堆积载体，所述堆积载体包括导电材料和绝缘材料的多个交替层，其中所述导电材料层中的至少一个耦合到所述触点之一 点的死亡 还公开了一种形成包装的方法和包括包括包装的计算装置的装置。