公开(公告)号：US09768067B2

公开(公告)日：2017-09-19

申请号：US15364160

申请日：2016-11-29

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu ,  Ying-Nan Wen ,  Shih-Yi Lee ,  Ho-Yin Yiu

IPC: H01L21/768 ,  H01L21/268 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L21/683 ,  H01L21/78 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/263 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L21/2633 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/43 ,  H01L24/45 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0233 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06135 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/432 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

公开(公告)号：US09721911B2

公开(公告)日：2017-08-01

申请号：US14931633

申请日：2015-11-03

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Shih-Yi Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/31 ,  H01L21/311 ,  H01L21/78 ,  H01L21/02 ,  G06F21/32 ,  H01L23/525

CPC classification number: H01L24/09 ,  G06F21/32 ,  H01L21/02013 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/08235 ,  H01L2224/08237 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface. The conductive pad is located on the first surface. The second surface has a first through hole to expose the conductive pad. The laser stopper is located on the conductive pad in the first through hole. The isolation layer is located on the second surface and in the first through hole. The isolation layer has a third surface opposite to the second surface, and has a second through hole to expose the laser stopper. The redistribution layer is located on the third surface, a sidewall of the second through hole, and the laser stopper in the second through hole. The conductive structure is located on the redistribution.

公开(公告)号：US09281243B2

公开(公告)日：2016-03-08

申请号：US14172832

申请日：2014-02-04

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu ,  Ying-Nan Wen

IPC: H01L23/495 ,  H01L21/78 ,  H01L23/00 ,  H01L23/552 ,  B81B7/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/78 ,  B81B7/0064 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/11 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A chip scale package structure includes a chip, a dam unit, a board body, a plurality of first conductors, an encapsulating glue, a plurality of first conductive layers, an isolation layer, and a plurality of first electrodes. The dam unit is disposed on the surface of the chip. The board body is located on the dam unit. The first conductors are respectively in electrical contact with the conductive pads of the chip. The encapsulating glue covers the surface of the chip, and the board body and the first conductors are packaged in the encapsulating glue. The first conductive layers are located on the surface of the encapsulating glue opposite to the chip and respectively in electrical contact with the first conductors. The isolation layer is located on the encapsulating glue and the first conductive layers. The first electrodes are respectively in electrical contact with the first conductive layers.

Abstract translation: 芯片级封装结构包括芯片，堤坝单元，板体，多个第一导体，封装胶，多个第一导电层，隔离层和多个第一电极。 大坝单元设置在芯片的表面上。 板体位于坝体上。 第一导体分别与芯片的导电焊盘电接触。 封装胶覆盖芯片的表面，并且板体和第一导体封装在封装胶中。 第一导电层位于与芯片相对的封装胶的表面上，分别与第一导体电接触。 隔离层位于封装胶和第一导电层上。 第一电极分别与第一导电层电接触。

公开(公告)号：US08872196B2

公开(公告)日：2014-10-28

申请号：US13720627

申请日：2012-12-19

Applicant: Xintec Inc.

Inventor： Po-Han Lee ,  Chien-Hung Liu

IPC: H01L31/12 ,  H01L31/18

CPC classification number: H01L31/12 ,  H01L31/1876

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a sensor region formed in the semiconductor substrate; a light emitting device disposed on the second surface of the semiconductor substrate; at least one first conducting bump disposed on the first surface of the semiconductor substrate and electrically connected to the sensor region; at least one second conducting bump disposed on the first surface of the semiconductor substrate and electrically connected to the light emitting device; and an insulating layer located on the semiconductor substrate to electrically insulate the semiconductor substrate from the at least one first conducting bump and the at least one second conducting bump.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 形成在所述半导体衬底中的传感器区域; 设置在所述半导体衬底的第二表面上的发光器件; 至少一个第一导电凸块，设置在所述半导体衬底的所述第一表面上并电连接到所述传感器区域; 设置在所述半导体衬底的所述第一表面上并电连接到所述发光器件的至少一个第二导电凸块; 以及绝缘层，其位于所述半导体衬底上以使所述半导体衬底与所述至少一个第一导电凸块和所述至少一个第二导电凸块电绝缘。

公开(公告)号：US08778798B1

公开(公告)日：2014-07-15

申请号：US14207247

申请日：2014-03-12

Applicant: Xintec Inc.

Inventor： Shu-Ming Chang ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

IPC: H01L21/44

CPC classification number: H01L21/50 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/92 ,  H01L24/93 ,  H01L24/94 ,  H01L33/62 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03825 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32052 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92142 ,  H01L2224/92143 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/1182 ,  H01L2224/03 ,  H01L2224/0382 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.

公开(公告)号：US09406578B2

公开(公告)日：2016-08-02

申请号：US14638219

申请日：2015-03-04

Applicant: XINTEC INC.

Inventor： Ying-Nan Wen ,  Chien-Hung Liu ,  Ho-Yin Yiu

IPC: H01L23/48 ,  H01L21/44 ,  H01L23/31 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/3114 ,  H01L21/268 ,  H01L21/31053 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/034 ,  H01L2224/0362 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/12042 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The semiconductor chip has an electronic component and a conductive pad that are electrically connected and disposed on an upper surface of the semiconductor chip. The first depression and first redistribution layer extend from the upper surface toward the lower surface of the semiconductor chip. The first redistribution layer and the conductive pad are electrically connected. The second depression and the second redistribution layer extends from the lower surface toward the upper surface and is in connection with the first depression through a connection portion. The second redistribution layer is electrically connected to the first redistribution layer through the connection portion. The packaging layer is disposed on the lower surface.

Abstract translation: 半导体封装包括半导体芯片，第一和第二凹陷，第一和第二再分布层和封装层。 半导体芯片具有电连接并设置在半导体芯片的上表面上的电子部件和导电焊盘。 第一凹陷部和第一再分布层从半导体芯片的上表面向下表面延伸。 第一再分配层和导电焊盘电连接。 第二凹陷和第二再分布层从下表面向上表面延伸并且通过连接部分与第一凹陷连接。 第二再分配层通过连接部分电连接到第一再分配层。 包装层设置在下表面上。

公开(公告)号：US09177919B2

公开(公告)日：2015-11-03

申请号：US14540460

申请日：2014-11-13

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu ,  Ying-Nan Wen

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/28

CPC classification number: H01L23/5386 ,  B81B7/0064 ,  B81B2207/096 ,  H01L21/561 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/29011 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48471 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package including a first substrate having a first surface and a second surface opposite thereto is provided. The first substrate has a micro-electric element and a plurality of conducting pads adjacent to the first surface. The first substrate has a plurality of openings respectively exposing a portion of each conducting pad. A second substrate is disposed on the first surface. An encapsulation layer is disposed on the first surface and covers the second substrate. A redistribution layer is disposed on the second surface and extends into the openings to electrically connect the conducting pads.

Abstract translation: 提供了包括具有第一表面和与其相对的第二表面的第一基板的芯片封装。 第一基板具有微电元件和与第一表面相邻的多个导电垫。 第一基板具有分别暴露每个导电垫的一部分的多个开口。 第二基板设置在第一表面上。 封装层设置在第一表面上并覆盖第二基板。 再分配层设置在第二表面上并延伸到开口中以电连接导电垫。