公开(公告)号：US20190057840A1

公开(公告)日：2019-02-21

申请号：US16107844

申请日：2018-08-21

Applicant: Applied Materials, Inc.

Inventor： Kenneth S. COLLINS ,  Michael R. RICE ,  Kartik RAMASWAMY ,  James D. CARDUCCI ,  Yue GUO ,  Olga REGELMAN

IPC: H01J37/32

CPC classification number: H01J37/32174 ,  H01J37/3211 ,  H01J37/32165 ,  H01J37/3244 ,  H01J37/32568

Abstract: Embodiments of the disclosure provide a plasma source assembly and process chamber design that can be used for any number of substrate processing techniques. The plasma source may include a plurality of discrete electrodes that are integrated with a reference electrode and a gas feed structure to generate a uniform, stable and repeatable plasma during processing. The plurality of discrete electrodes include an array of electrodes that can be biased separately, in groups or all in unison, relative to a reference electrode. The plurality of discrete electrodes may include a plurality of conductive rods that are positioned to generate a plasma within a processing region of a process chamber. The plurality of discrete electrodes is provided RF power from standing or traveling waves imposed on a power distribution element to which the electrodes are connected.

公开(公告)号：US20190035606A1

公开(公告)日：2019-01-31

申请号：US15867082

申请日：2018-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Jin Yoo ,  Sang Ki Nam ,  Kwang-Youb Heo ,  Jehun Woo ,  Sang-Heon Lee ,  Masahiko Tomita ,  Vasily Pashkovskiy

IPC: H01J37/32 ,  H01L21/027 ,  H01L21/67 ,  H01L21/683 ,  H01L21/311

CPC classification number: H01L21/3065 ,  H01J37/32128 ,  H01J37/32146 ,  H01J37/32165 ,  H01J37/32174 ,  H01J37/32724 ,  H01J2237/334 ,  H01L21/0273 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/67069 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/67248 ,  H01L21/6831 ,  H01L21/6833

Abstract: In a plasma processing method, a substrate is loaded onto a substrate electrode within a chamber, the substrate having an object layer to be etched thereon. A plasma generating power output is applied to form plasma within the chamber. A first bias power output is applied to the substrate electrode to perform a first etch stage on the object layer. A second bias power output having a nonsinusoidal voltage waveform is applied to the substrate electrode to perform a second etch stage on the object layer.

公开(公告)号：US20180342401A1

公开(公告)日：2018-11-29

申请号：US15988215

申请日：2018-05-24

Applicant: TOKYO ELECTRON LIMITED

Inventor： Kosuke KOIWA

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/3065

CPC classification number: H01L21/31127 ,  H01J37/32091 ,  H01J37/32165 ,  H01J37/3244 ,  H01J37/32642 ,  H01J37/32715 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136

Abstract: An etching method includes a loading step of loading into a chamber a target substrate in which a mask film is laminated on an organic film; a first etching step of etching the organic film below the mask film by plasma of a processing gas in which a flow rate ratio of a second gas containing sulfur to a first gas containing oxygen is set to a first flow rate ratio; and a second etching step of further etching the organic film by plasma of a processing gas in which a flow rate ratio of the second gas to the first gas is set to a second flow rate ratio different from the first flow rate ratio. The first etching step and the second etching step are alternately performed multiple times.

公开(公告)号：US20180301320A1

公开(公告)日：2018-10-18

申请号：US16013811

申请日：2018-06-20

Applicant: Lam Research Corporation

Inventor： Zhigang Chen ,  Alexei Marakhtanov ,  John Patrick Holland

IPC: H01J37/32

CPC classification number: H01J37/32146 ,  H01J37/32082 ,  H01J37/32165 ,  H01J37/32174 ,  H01J37/32183 ,  H01J37/32678 ,  H01J2237/327

Abstract: Systems and methods for controlling a process applied to a substrate within a plasma chamber are described. The systems and methods include generating and supplying odd harmonic signals and summing the odd harmonic signals to generate an added signal. The added signal is supplied to an electrode within the plasma chamber for processing the substrate. The use of odd harmonic signals facilitates high aspect ratio etching of the substrate.

公开(公告)号：US20180277405A1

公开(公告)日：2018-09-27

申请号：US15687950

申请日：2017-08-28

Applicant: HITACHI KOKUSAI ELECTRIC INC.

Inventor： Satoshi SHIMAMOTO ,  Hiroshi ASHIHARA ,  Kazuyuki TOYODA ,  Naofumi OHASHI

IPC: H01L21/67 ,  H01L21/677 ,  C23C16/52 ,  C23C16/50 ,  C23C16/24

CPC classification number: H01L21/67207 ,  C23C16/24 ,  C23C16/345 ,  C23C16/402 ,  C23C16/4584 ,  C23C16/50 ,  C23C16/505 ,  C23C16/517 ,  C23C16/52 ,  H01J37/32082 ,  H01J37/32165 ,  H01J37/32449 ,  H01J37/32899 ,  H01L21/67017 ,  H01L21/6719 ,  H01L21/67748 ,  H01L21/67754 ,  H01L21/68764 ,  H01L21/68771 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11582

Abstract: A substrate processing apparatus includes: a single frequency process chamber installed inside a process module and for processing a substrate on which an insulating film is formed; a two-frequency process chamber installed adjacent to the single frequency process chamber inside the process module and for processing the substrate processed in the single frequency process chamber; a gas supply part configured to supply a silicon-containing gas containing at least silicon and an impurity to each of the process chambers; a plasma generation part connected to each of the process chambers; an ion control part connected to the two-frequency process chamber; a substrate transfer part installed inside the process module and configured to transfer the substrate between the single frequency process chamber and the two-frequency process chamber; and a controller configured to control at least the gas supply part, the plasma generation part, the ion control part, and the substrate transfer part.

公开(公告)号：US20180190474A1

公开(公告)日：2018-07-05

申请号：US15905908

申请日：2018-02-27

Applicant: Tokyo Electron Limited

Inventor： Koichi Nagami

IPC: H01J37/32

CPC classification number: H01J37/32174 ,  H01J37/32091 ,  H01J37/32165 ,  H01J37/32183 ,  H01J37/32449 ,  H01J37/32577

Abstract: In a plasma processing apparatus, an operation unit configured to calculate a parameter including any one of a load impedance, a load resistance and a load reactance of a high frequency power supply and a reflection wave coefficient of a high frequency power, and a controller configured to sequentially perform multiple cycles, each having plural stages which are performed in sequence. The controller is configured to control a setting of the high frequency power supplied to an electrode to be changed at a time point when the parameter exceeds a threshold value after a processing gas is changed. The changing of the setting of the high frequency power includes changing a power level of the high frequency power and/or changing the high frequency power from one of a continuous wave and a pulse-modulated high frequency power to the other thereof.

公开(公告)号：US20180166256A1

公开(公告)日：2018-06-14

申请号：US15882429

申请日：2018-01-29

Applicant: Lam Research Corporation

Inventor： Alexei Marakhtanov ,  Rajinder Dhindsa

IPC: H01J37/32

CPC classification number: H01J37/32091 ,  H01J37/32165

Abstract: Circuits, methods, chambers, systems, and computer programs are presented for processing wafers. A wafer processing apparatus includes top and bottom electrodes inside a processing chamber; a first, second, third, and fourth radio frequency (RF) power sources; and one or more resonant circuits. The first, second, and third RF power sources are coupled to the bottom electrode. The top electrode may be coupled to the fourth RF power source, to electrical ground, or to the one or more resonant circuits. Each of the one or more resonant circuits, which are coupled between the top electrode and electrical ground, include a tune-in element operable to vary a frequency-dependent impedance presented by the resonant circuit. The wafer processing apparatus is configurable to select the RF power sources for wafer processing operations, as well as the connections to the top electrode in order to provide plasma and etching uniformity for the wafer.

公开(公告)号：US09997374B2

公开(公告)日：2018-06-12

申请号：US15375405

申请日：2016-12-12

Applicant: Tokyo Electron Limited

Inventor： Ryohei Takeda ,  Sho Tominaga ,  Yoshinobu Ooya

IPC: H01L21/311 ,  H01L21/02 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01J37/32165 ,  H01J37/3244 ,  H01J37/32568 ,  H01J37/32715 ,  H01J2237/334

Abstract: An etching method performed by an etching apparatus includes a first process of causing a first high-frequency power supply to output a first high-frequency power with a first frequency and causing a second high-frequency power supply to output a second high-frequency power with a second frequency lower than the first frequency in a cryogenic environment where the temperature of a wafer is −35° C. or lower, to generate plasma from a hydrogen-containing gas and a fluorine-containing gas and to etch, with the plasma, a multi-layer film of silicon dioxide and silicon nitride and a single-layer film of silicon dioxide that are formed on the wafer; and a second process of stopping the output of the second high-frequency power supply. The first process and the second process are repeated multiple times, and the first process is shorter in time than the second process.

公开(公告)号：US09978563B2

公开(公告)日：2018-05-22

申请号：US15266397

申请日：2016-09-15

Applicant: Tokyo Electron Limited

Inventor： Vinh Luong ,  Akiteru Ko

IPC: H01L21/302 ,  H01J37/32 ,  H01L21/027 ,  H01L21/3105 ,  B81C1/00

CPC classification number: H01J37/32082 ,  B81C1/00531 ,  H01J37/32165 ,  H01J37/3244 ,  H01L21/0274 ,  H01L21/31058 ,  H01L21/31116

Abstract: Provided is a method of patterning a layer on a substrate using an integration scheme, the method comprising: disposing a substrate having a structure pattern layer, a neutral layer, and an underlying layer, the structure pattern layer comprising a first material and a second material; performing a first treatment process using a first process gas mixture to form a first pattern, the first process gas comprising a mixture of CxHyFz and argon; performing a second treatment process using a second process gas mixture to form a second pattern, the second process gas comprising a mixture of low oxygen-containing gas and argon; concurrently controlling selected two or more operating variables of the integration scheme in order to achieve target integration objectives.

公开(公告)号：US09947513B2

公开(公告)日：2018-04-17

申请号：US15605831

申请日：2017-05-25

Applicant: Lam Research Corporation

Inventor： John C. Valcore, Jr. ,  Bradford J. Lyndaker ,  Andrew S. Fong

IPC: H01J37/32 ,  H05H1/46

CPC classification number: H01J37/32165 ,  H01J37/32174 ,  H01J37/32183 ,  H05H1/46 ,  H05H2001/4682

Abstract: Systems and methods for performing edge ramping are described. A system includes a base RF generator for generating a first RF signal. The first RF signal transitions from one state to another. The transition from one state to another of the first RF signal results in a change in plasma impedance. The system further includes a secondary RF generator for generating a second RF signal. The second RF signal transitions from one state to another to stabilize the change in the plasma impedance. The system includes a controller coupled to the secondary RF generator. The controller is used for providing parameter values to the secondary RF generator to perform edge ramping of the second RF signal when the second RF signal transitions from one state to another.