公开(公告)号：US11784082B2

公开(公告)日：2023-10-10

申请号：US18092337

申请日：2023-01-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H10B20/20

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1579 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/30105 ,  H10B12/05 ,  H10B20/20

Abstract: A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said first transistors controls power delivery for at least one of said second transistor, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

公开(公告)号：US11763864B2

公开(公告)日：2023-09-19

申请号：US17948225

申请日：2022-09-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: G11C7/18 ,  G11C7/12 ,  G11C16/24 ,  G11C16/04 ,  H10B43/20

CPC classification number: G11C7/18 ,  G11C7/12 ,  G11C16/0466 ,  G11C16/24 ,  H10B43/20

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the plurality of bit-line pillars are vertically oriented, where the channel is horizontally oriented, where a plurality of the channels are connected to a body pillar, and where the body pillar is at least temporary connected to a negative bias.

公开(公告)号：US11757030B2

公开(公告)日：2023-09-12

申请号：US18125053

申请日：2023-03-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L29/78 ,  G11C16/02 ,  G11C11/404 ,  G11C11/4097 ,  H10B10/00 ,  H10B12/00 ,  H10B43/20 ,  H10B69/00 ,  H10B63/00 ,  H01L23/522 ,  H01L23/528 ,  G11C11/412 ,  G11C16/04

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C16/02 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/7841 ,  H10B10/12 ,  H10B12/20 ,  H10B43/20 ,  H10B63/30 ,  H10B69/00 ,  G11C11/412 ,  G11C16/0483 ,  G11C2213/71

Abstract: A semiconductor device, the device including: a first silicon layer including first single crystal silicon; an isolation layer disposed over the first silicon layer; a first metal layer disposed over the isolation layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the isolation layer includes an oxide to oxide bond surface, where the plurality of transistors include a second single crystal silicon region; and a third metal layer disposed over the first level, where a typical first thickness of the third metal layer is at least 50% greater than a typical second thickness of the second metal layer.

公开(公告)号：US11735501B1

公开(公告)日：2023-08-22

申请号：US18136336

申请日：2023-04-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/768 ,  H01L23/48 ,  H01L27/06 ,  H01L27/088 ,  H01L29/732 ,  H01L27/118 ,  H01L29/10 ,  H01L29/808 ,  H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L21/74 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H01L23/544 ,  H01L23/34 ,  H01L23/50 ,  H10B63/00

CPC classification number: H01L23/481 ,  H01L21/743 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66704 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H01L27/0623 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152 ,  H10B63/30 ,  H10B63/845

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where at least one of the transistors includes a four sided gate.

公开(公告)号：US11711928B2

公开(公告)日：2023-07-25

申请号：US18105856

申请日：2023-02-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L23/544 ,  H01L25/065

CPC classification number: H10B80/00 ,  H01L23/544 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145

Abstract: A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; and a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells includes at least one second transistor, where the control circuits control access to the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least a portion of the array of memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.

公开(公告)号：US11694922B2

公开(公告)日：2023-07-04

申请号：US18102710

申请日：2023-01-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: B23K26/36 ,  H01L21/762 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12 ,  H01L27/15 ,  H01L25/18 ,  G02B6/12 ,  H01L29/66 ,  H01L23/00

CPC classification number: H01L21/76275 ,  G02B6/12002 ,  G02B6/12004 ,  H01L21/84 ,  H01L25/18 ,  H01L27/12 ,  H01L27/15 ,  H01L29/4236 ,  H01L29/66477 ,  G02B2006/12061 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05124 ,  H01L2224/05655 ,  H01L2224/16145

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one processor, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US20230197741A1

公开(公告)日：2023-06-22

申请号：US18110362

申请日：2023-02-15

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L27/146 ,  H01L33/16 ,  H01L25/075 ,  H01L27/15 ,  H01L33/62 ,  G16H15/00 ,  G06F40/40 ,  G06F40/186 ,  G06F3/01 ,  G10L15/26 ,  H01L25/16

CPC classification number: H01L27/14603 ,  H01L33/16 ,  H01L25/0756 ,  H01L27/156 ,  H01L33/62 ,  G16H15/00 ,  G06F40/40 ,  G06F40/186 ,  G06F3/013 ,  G10L15/26 ,  H01L25/167

Abstract: A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes a plurality of LED driving circuits; a second level including a first plurality of light emitting diodes (LEDs), where the second level is disposed on top of the first level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the second level includes a plurality of bond pads, where the bonding structure includes oxide to oxide bonding.

公开(公告)号：US20230197573A1

公开(公告)日：2023-06-22

申请号：US18109254

申请日：2023-02-13

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/48 ,  H01L27/06 ,  H01L27/088 ,  H01L29/732 ,  H01L27/118 ,  H01L29/10 ,  H01L29/808 ,  H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L21/74 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H01L23/544 ,  H01L23/34 ,  H01L23/50

CPC classification number: H01L23/481 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/732 ,  H01L27/11807 ,  H01L29/1066 ,  H01L29/808 ,  H01L29/66825 ,  H01L27/0207 ,  H01L29/66901 ,  H01L29/7841 ,  H01L29/66272 ,  H01L21/743 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H01L23/544 ,  H01L29/66704 ,  H01L23/34 ,  H01L23/50 ,  H01L27/0886 ,  H01L27/0623 ,  H01L2924/16152 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/13062 ,  H01L2924/12032 ,  H01L2924/1305 ,  H10B63/30

Abstract: A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via includes contact with at least one of the plurality of transistors.

公开(公告)号：US20230187256A1

公开(公告)日：2023-06-15

申请号：US18106757

申请日：2023-02-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/84 ,  H01L21/743 ,  H01L21/8221 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/823828 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/10 ,  H01L27/092 ,  H01L27/105 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/11807 ,  H01L27/11898 ,  H01L29/78 ,  H01L29/792 ,  H01L29/4236 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H10B10/00 ,  H10B10/125 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B12/053 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L2924/13062

Abstract: A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing a second lithography step on the third level; perform processing steps to form first memory cells within the second level and second memory cells within the third level, where first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and deposit a gate electrode for the second and the third transistors simultaneously.

公开(公告)号：US11615228B1

公开(公告)日：2023-03-28

申请号：US18090134

申请日：2022-12-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F30/392 ,  G06F30/394

Abstract: A method of designing a 3D Integrated Circuit, the method including: partitioning at least one design into at least two levels, a first level and a second level; providing connections placement data of the second level, where the connections include planned connections between the first level and the second level; performing a placement of the first level using a placer executed by a computer, where the placement of the first level is based on the connections placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; and performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool.