公开(公告)号：US20100119050A1

公开(公告)日：2010-05-13

申请号：US12510343

申请日：2009-07-28

Applicant: Ching-Chuan Kuo ,  Shih-Chia Wang ,  Ping- Hsui Wu ,  Chien-Che Huang ,  Hu-Chi Chen

Inventor： Ching-Chuan Kuo ,  Shih-Chia Wang ,  Ping- Hsui Wu ,  Chien-Che Huang ,  Hu-Chi Chen

IPC: H04M3/42

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09763 ,  H05K2203/0152 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: An auto provision system and method for a customer premises equipment (CPE) include: connecting a CPE to a provision platform through a network; authenticating the CPE by the provision platform and generating and transmitting a corresponding setting file to the CPE by the provision platform; and the CPE updating the configuration thereof by using the received setting file, thereby saving manual costs for ISPs (Internet Service Providers), ensuring ease of use, and enhancing information security.

Abstract translation: 用于客户驻地设备（CPE）的自动提供系统和方法包括：通过网络将CPE连接到提供平台; 通过提供平台认证CPE，并通过提供平台生成并发送相应的设置文件到CPE; 并且CPE通过使用接收的设置文件来更新其配置，从而节省ISP（因特网服务提供商）的手动成本，确保易于使用和增强信息安全性。

公开(公告)号：US07705423B2

公开(公告)日：2010-04-27

申请号：US11523270

申请日：2006-09-19

Applicant: Madhavan Swaminathan ,  Ege Engin ,  Prathap Muthana ,  Krishna Srinivasan

Inventor： Madhavan Swaminathan ,  Ege Engin ,  Prathap Muthana ,  Krishna Srinivasan

IPC: H01L29/00

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/3011 ,  H05K1/162 ,  H05K2201/09763 ,  H05K2201/10674 ,  Y10S257/924

Abstract: One embodiment of the present invention provides advice for providing a low noise power supply package to an integrated circuit comprising a semiconductor die, input/output power supply terminals, and an array of embedded ceramic capacitors selected from discrete, planar and combinations thereof wherein said capacitors are placed in the locations selected from within the perimeter of the shadow of the semiconductor die, partially within the perimeter of the shadow of the semiconductor die, near the perimeter of the shadow of the semiconductor die, and combinations thereof.

Abstract translation: 本发明的一个实施例提供了向包括半导体管芯，输入/输出电源端子以及选自离散，平面和组合的嵌入式陶瓷电容器阵列的集成电路提供低噪声电源封装的建议，其中所述电容器 被放置在从半导体管芯的阴影的周边中选择的位置，部分地在半导体管芯的阴影的周边内，靠近半导体管芯的阴影的周边，以及它们的组合。

公开(公告)号：US20100085680A1

公开(公告)日：2010-04-08

申请号：US12514823

申请日：2007-12-11

Applicant: John D. Summers

Inventor： John D. Summers

IPC: H01G4/224 ,  C08G69/26 ,  H01L21/56

CPC classification number: H05K1/162 ,  C08L79/08 ,  C09D179/08 ,  H05K3/1291 ,  H05K2201/0154 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126

Abstract: This invention relates to compositions, and the use of such compositions for protective coatings, particularly of electronic devices. The invention concerns fired-on-foil ceramic capacitors coated with a composite encapsulant and embedded in a printed wiring board.

Abstract translation: 本发明涉及组合物，以及这些组合物用于保护涂层，特别是电子器件的用途。 本发明涉及涂覆有复合密封剂并嵌入印刷线路板的烧制箔陶瓷电容器。

公开(公告)号：US20100059858A1

公开(公告)日：2010-03-11

申请号：US12590547

申请日：2009-11-10

Applicant: John J. Tang ,  Xiang Yin Zeng ,  Jiangqi He ,  Ding Hai

Inventor： John J. Tang ,  Xiang Yin Zeng ,  Jiangqi He ,  Ding Hai

IPC: H01L29/92

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48472 ,  H01L2224/49 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H05K1/111 ,  H05K1/113 ,  H05K1/162 ,  H05K3/28 ,  H05K2201/0187 ,  H05K2201/09436 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.

公开(公告)号：US07614142B2

公开(公告)日：2009-11-10

申请号：US12068272

申请日：2008-02-05

Applicant: Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

IPC: H05K3/36 ,  H01L23/29

CPC classification number: H01L23/50 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599

Abstract: A method for fabricating an interposer includes: forming on one primary surface of a first substrate a thin-film capacitor including a first capacitor electrode, a crystalline capacitor dielectric film formed on the first electrode and a second capacitor electrode formed on the dielectric film; and forming on the primary surface of the first substrate and the capacitor a first layer as semi-cured, and a first partial electrode to be a part of a through-electrode, buried in the first resin layer and electrically connected to the first electrode or the second electrode. The method further includes cutting an upper part of the first partial electrode and an upper part of the first resin layer with a cutting tool; forming on one primary surface of a second substrate a second resin layer as semi-cured, and a second partial electrode to be a part of the through-electrode, buried in the second resin layer and disposed in alignment with the first partial electrode; cutting an upper part of the second partial electrode and an upper part of the second resin layer with a cutting tool; making thermal processing with the first resin layer and the second resin layer in close contact with each other to adhere the first resin and the second resin layer to each other while jointing the first and second partial electrodes to each other; removing the first substrate; forming on said one primary surface of the second substrate a third resin layer, covering the thin-film capacitor, burying a third partial electrode to be a part of the through-electrode in the third resin layer, supporting the third resin layer by a supporting substrate; and removing the second substrate.

Abstract translation: 一种用于制造插入件的方法，包括：在第一基板的一个主表面上形成薄膜电容器，薄膜电容器包括第一电容器电极，形成在第一电极上的晶体电容器电介质膜和形成在电介质膜上的第二电容器电极; 并且在第一基板和电容器的主表面上形成半固化的第一层，以及作为通孔的一部分的第一部分电极，埋入第一树脂层中并电连接到第一电极或 第二电极。 该方法还包括用切割工具切割第一部分电极的上部和第一树脂层的上部; 在第二基板的一个主表面上形成半固化的第二树脂层和作为所述通孔的一部分的第二部分电极，所述第二部分电极埋入所述第二树脂层中并与所述第一部分电极对准; 用切割工具切割第二部分电极的上部和第二树脂层的上部; 使第一树脂层和第二树脂层彼此紧密接触进行热处理，以将第一和第二部分电极彼此接合，使第一树脂和第二树脂层彼此粘合; 去除第一衬底; 在所述第二基板的所述一个主表面上形成覆盖所述薄膜电容器的第三树脂层，在所述第三树脂层中埋设作为所述贯通电极的一部分的第三部分电极，通过支撑所述第三树脂层 基质; 并移除第二基板。

公开(公告)号：US07588992B2

公开(公告)日：2009-09-15

申请号：US11152328

申请日：2005-06-14

Applicant: Yongki Min

Inventor： Yongki Min

IPC: H01L21/461

CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K1/162 ,  H05K3/025 ,  H05K3/4652 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2203/0384 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A thin-film capacitor assembly includes a first metal bottom electrode, a dielectric layer, a second metal etch-stop layer, and a subsequent metal top electrode. The first metal bottom electrode is in contact with the dielectric layer. The second metal etch-stop layer is in contact with the dielectric layer. The subsequent metal top electrode is in contact with the second metal etch-stop layer. Processing of the thin-film capacitor assembly includes totally removing a stiffener after assembling the first metal bottom electrode as a layer to the dielectric layer and the second metal etch-stop layer. The stiffener is removed from above and on the second metal etch-stop layer. The thin-film capacitor assembly is laminated to a mounting substrate.

Abstract translation: 薄膜电容器组件包括第一金属底电极，电介质层，第二金属蚀刻停止层和随后的金属顶电极。 第一金属底电极与电介质层接触。 第二金属蚀刻停止层与电介质层接触。 随后的金属顶电极与第二金属蚀刻停止层接触。 薄膜电容器组件的处理包括在将第一金属底电极组装成介电层和第二金属蚀刻停止层之后，完全去除加强件。 加强件从第二金属蚀刻停止层上方和第二金属蚀刻停止层移除。 将薄膜电容器组件层压到安装基板上。

公开(公告)号：US20090219670A1

公开(公告)日：2009-09-03

申请号：US12394995

申请日：2009-02-27

Applicant: Takeo TAKAHASHI ,  Xiaoyu Mi ,  Satoshi Ueda

Inventor： Takeo TAKAHASHI ,  Xiaoyu Mi ,  Satoshi Ueda

IPC: H01G4/06 ,  B05D5/12

CPC classification number: H01G4/06 ,  H01G13/00 ,  H01L27/016 ,  H01L28/10 ,  H01L28/40 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/4007 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4644 ,  H05K2201/09763 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49126

Abstract: A method of fabricating an electronic device includes selectively forming a glass layer on a ceramic substrate by printing, baking the glass layer, and forming a capacitor on the glass layer, the capacitor including metal electrodes and a dielectric layer interposed between the metal electrodes.

Abstract translation: 一种制造电子器件的方法包括通过印刷，烘烤玻璃层和在玻璃层上形成电容器，在陶瓷基片上选择性地形成玻璃层，电容器包括金属电极和置于金属电极之间的电介质层。

公开(公告)号：US07571536B2

公开(公告)日：2009-08-11

申请号：US11698423

申请日：2007-01-26

Applicant: David Ross McGregor

Inventor： David Ross McGregor

IPC: H01C17/28

CPC classification number: H05K1/167 ,  H01L2924/19105 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/1453 ,  Y10T29/49101 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A method of making capacitive/resistive devices provides both resistive and capacitive functions. The capacitive/resistive devices may be embedded within a layer of a printed wiring board. Embedding the capacitive/resistive devices conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability.

Abstract translation: 制造电容/电阻器件的方法提供电阻和电容功能。 电容/电阻器件可以嵌入印刷线路板的层内。 嵌入电容/电阻器件节省了电路板表面的空间，并减少了焊接连接的数量，从而提高了可靠性。

公开(公告)号：US20090073667A1

公开(公告)日：2009-03-19

申请号：US12230872

申请日：2008-09-05

Applicant: Yul-Kyo Chung ,  Sung Yi ,  Soon-Gyu Yim ,  Seog-Moon Choi ,  Jin-Gu Kim ,  Young-Do Kweon

Inventor： Yul-Kyo Chung ,  Sung Yi ,  Soon-Gyu Yim ,  Seog-Moon Choi ,  Jin-Gu Kim ,  Young-Do Kweon

IPC: H05K1/18 ,  H01L27/06

CPC classification number: H05K1/162 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/25 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/19041 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip.

Abstract translation: 公开了一种半导体芯片封装和具有嵌入式半导体芯片封装的印刷电路板。 半导体芯片封装可以包括在一侧形成有至少一个芯片焊盘的半导体芯片和形成在半导体芯片的另一侧上的电容器。

公开(公告)号：US20080253097A1

公开(公告)日：2008-10-16

申请号：US11969606

申请日：2008-01-04

Applicant: Shuichi KAWANO

Inventor： Shuichi KAWANO

IPC: H05K1/11 ,  H05K1/16

CPC classification number: H05K1/162 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/3436 ,  H05K3/423 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/0733 ,  H01L2924/00

Abstract: An interposer is constructed with a substrate body having first and second through-holes, a capacitor formed by a laminating dielectric layer and a second electrode portion on a first electrode portion, which is structured on inner surfaces of first and second through-holes and on the first surface of the substrate body. An insulation layer is formed by filling insulation material in the space within the first through-hole surrounded by second electrode portion, and a first post passes through the insulation layer, one end being electrically connected to the first electrode portion, while the first post is electrically insulated from the second electrode portion. Furthermore, a second post is formed in the second through-hole, and is connected to the second electrode portion at its peripheral surface while being electrically insulated from the first electrode portion.

Abstract translation: 内插件由具有第一通孔和第二通孔的基板本体构成，电容器由第一电极部分上的叠层电介质层和第二电极部分构成，该第一电极部分构造在第一通孔和第二通孔的内表面上， 衬底主体的第一表面。 通过在由第二电极部包围的第一通孔内的空间内填充绝缘材料形成绝缘层，第一柱通过绝缘层，一端电连接到第一电极部分，而第一柱为 与第二电极部分电绝缘。 此外，第二通孔形成在第二通孔中，并且在与第一电极部分电绝缘的同时在其外周面与第二电极部分连接。