公开(公告)号：US09305846B2

公开(公告)日：2016-04-05

申请号：US14599873

申请日：2015-01-19

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/02 ,  H01L21/266 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

公开(公告)号：US09293532B2

公开(公告)日：2016-03-22

申请号：US14751542

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US09293520B2

公开(公告)日：2016-03-22

申请号：US13845560

申请日：2013-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Geng Wang ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC: H01L21/70 ,  H01L49/02 ,  H01L21/762 ,  H01L21/74 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

Abstract translation: 提供一种半导体结构，其包括在基底半导体层上包含外延生长的半导体层的材料堆叠，外延生长的半导体层上的电介质层和存在于电介质层上的上半导体层。 存在从上半导体层通过电介质层延伸到与外延生长的半导体层接触的电容器。 电容器包括存在于沟槽的侧壁上的节点电介质和填充沟槽的至少一部分的上电极。 在从上半导体层通过电介质层和外延半导体层延伸到基底半导体层的掺杂区域的接触沟槽中存在衬底接触。 还提供了通过沟槽的侧壁接触基底半导体层的衬底接触。 还提供了形成上述结构的方法。

公开(公告)号：US20160079397A1

公开(公告)日：2016-03-17

申请号：US14948977

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Eric C. Harley ,  Terence B. Hook ,  Ali Khakifirooz ,  Henry K. Utomo ,  Reinaldo A. Vega

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/785

Abstract: A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions.

Abstract translation: 形成由半导体层的顶表面悬挂并由栅极结构支撑的半导体鳍片。 在半导体层的顶表面和栅极结构之间形成绝缘体层。 形成栅极间隔物，通过各向异性蚀刻去除半导体鳍片的物理暴露部分。 随后，可以用锥形蚀刻绝缘体层的物理暴露部分。 或者，可以在绝缘体层的各向异性蚀刻之前形成一次性间隔件。 跨过栅极结构的电介质层中的两个开口之间的横向距离大于栅极间隔物的外侧壁之间的横向距离。 可以进行半导体材料的选择性沉积以形成凸起的活性区域。

公开(公告)号：US09281390B2

公开(公告)日：2016-03-08

申请号：US13964612

申请日：2013-08-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chandrasekara Kothandaraman ,  Chengwen Pei

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/78 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792 ,  H01L27/105 ,  H01L21/8234

CPC classification number: H01L29/78 ,  H01L21/28282 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

Abstract translation: 提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和 半导体衬底上的第二金属栅电极。 在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。 蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质 到第二金属栅电极的侧壁。

公开(公告)号：US09276002B2

公开(公告)日：2016-03-01

申请号：US14734310

申请日：2015-06-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Qizhi Liu ,  Edward J. Nowak ,  Jed H. Rankin

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L27/10826 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a bulk silicon finFET and methods of forming the same. An IC structure according to the present disclosure can include: a bulk substrate; a finFET located on a first region of the bulk substrate; and a layered dummy structure located on a second region of the bulk substrate, wherein the layered dummy structure includes a first crystalline semiconductive layer, a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the first crystalline semiconductive layer comprises a material distinct from the second crystalline semiconductive layer, and a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the material distinct from the second crystalline semiconductive layer.

Abstract translation: 本公开通常提供具有体硅片finFET的集成电路（IC）结构及其形成方法。 根据本公开的IC结构可以包括：体基板; 位于所述本体衬底的第一区域上的鳍状物FET; 以及分层虚拟结构，其位于所述本体衬底的第二区域上，其中所述分层虚拟结构包括第一晶体半导体层，位于所述第一晶体半导体层上的第二晶体半导体层，其中所述第一晶体半导体层包括不同的材料 以及位于所述第二晶体半导体层上的第三晶体半导体层，其中所述第三晶体半导体层包括与所述第二晶体半导体层不同的材料。

公开(公告)号：US09251978B2

公开(公告)日：2016-02-02

申请号：US13875394

申请日：2013-05-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu ,  Zhen Zhang

IPC: G01N27/404 ,  H01H29/02 ,  G01N33/00 ,  G01N15/10 ,  G01N27/327 ,  G01N27/447

CPC classification number: H01H29/02 ,  G01N15/1031 ,  G01N27/3278 ,  G01N27/404 ,  G01N27/44795 ,  G01N33/0009 ,  Y10T29/49117

Abstract: Electromechanical sensors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical sensor includes the following steps. A back gate is formed on a substrate. A gate dielectric is deposited over the back gate. An intermediate layer is formed on the back gate having a micro-fluidic channel formed therein. Top electrodes are formed above the micro-fluidic channel. One or more Janus components are placed in the micro-fluidic channel, wherein each of the Janus components has a first portion having an electrically conductive material and a second portion having an electrically insulating material. The micro-fluidic channel is filled with a fluid. The electrically insulating material has a negative surface charge at a pH of the fluid and an isoelectric point at a pH less than the pH of the fluid.

Abstract translation: 提供采用Janus微/纳米组件的机电传感器及其制造技术。 一方面，制造机电传感器的方法包括以下步骤。 在基板上形成背栅。 栅极电介质沉积在背栅上。 在背栅上形成中间层，其中形成有微流体通道。 顶部电极形成在微流体通道上方。 一个或多个Janus部件被放置在微流体通道中，其中Janus部件中的每一个具有具有导电材料的第一部分和具有电绝缘材料的第二部分。 微流体通道充满流体。 电绝缘材料在流体的pH下具有负的表面电荷，并且在pH小于流体的pH的pH下具有等电点。

公开(公告)号：US09240355B2

公开(公告)日：2016-01-19

申请号：US14705397

申请日：2015-05-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L21/84 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/861

Abstract: An electrical device including a first conductivity semiconductor device present in a first semiconductor device region of an SOI substrate, and a second conductivity semiconductor device present in a second semiconductor device region of the SOI substrate. The electrical device also includes a diode present within a diode region of the SOI substrate that includes a first doped layer of a first conductivity semiconductor material that is present on an SOI layer of the SOI substrate. The first doped layer includes a first plurality of protrusions extending from a first connecting base portion. The semiconductor diode further includes a second doped layer of the second conductivity semiconductor material present over the first doped layer. The second doped layer including a second plurality of protrusions extending from a second connecting base portion. The second plurality of protrusions is present between and separating the first plurality of protrusions.

Abstract translation: 一种电气装置，包括存在于SOI衬底的第一半导体器件区域中的第一导电半导体器件和存在于SOI衬底的第二半导体器件区域中的第二导电半导体器件。 电子器件还包括存在于SOI衬底的二极管区域内的二极管，其包括存在于SOI衬底的SOI层上的第一导电半导体材料的第一掺杂层。 第一掺杂层包括从第一连接基部延伸的第一多个突起。 半导体二极管还包括存在于第一掺杂层上的第二导电半导体材料的第二掺杂层。 第二掺杂层包括从第二连接基部延伸的第二多个突起。 第二多个突起存在于并分离第一多个突起之间。

公开(公告)号：US20160005733A1

公开(公告)日：2016-01-07

申请号：US14855881

申请日：2015-09-16

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Michael Wedlake ,  Xiuyu Cai ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7833

Abstract: One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure.

Abstract translation: 所公开的一个说明性装置尤其包括被隔离区隔开的第一和第二有源区，分别位于第一和第二有源区上方的第一和第二置换栅极结构以及位于隔离区上方的栅极配准结构 ，其中所述栅极配准结构包括位于所述隔离区域上方的绝缘材料层和抛光停止层，并且其中所述第一替换栅极结构的第一端表面邻接并接合所述栅极配准结构的第一侧表面， 第二替换栅极结构的端面邻接并接合栅极配准结构的第二侧表面。

公开(公告)号：US09224822B2

公开(公告)日：2015-12-29

申请号：US14023007

申请日：2013-09-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/20 ,  H01L21/36 ,  H01L29/36 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/36 ,  H01L21/02529 ,  H01L21/02532 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: A layer of a silicon germanium alloy containing 30 atomic percent or greater germanium and containing substitutional carbon is grown on a surface of a semiconductor layer. The presence of the substitutional carbon in the layer of silicon germanium alloy compensates the strain of the silicon germanium alloy, and suppresses defect formation. Placeholder semiconductor fins are then formed to a desired dimension within the layer of silicon germanium alloy and the semiconductor layer. The placeholder semiconductor fins will relax for the most part, while maintaining strain in a lengthwise direction. An anneal is then performed which may either remove the substitutional carbon from each placeholder semiconductor fin or move the substitutional carbon into interstitial sites within the lattice of the silicon germanium alloy. Free-standing permanent semiconductor fins containing 30 atomic percent or greater germanium, and strain in the lengthwise direction are provided.

Abstract translation: 在半导体层的表面上生长含有30原子％以上的锗并含有取代碳的硅锗合金层。 硅锗合金层中的取代碳的存在补偿了硅锗合金的应变，并抑制了缺陷的形成。 然后将占位半导体散热片形成为硅锗合金层和半导体层内所需的尺寸。 占位半导体鳍片大部分放松，同时保持长度方向的应变。 然后进行退火，其可以从每个占位符半导体鳍去除取代的碳，或者将取代的碳移动到硅锗合金的晶格内的间隙位置。 提供含有30原子％以上的锗的独立的永久性半导体散热片，并且在长度方向上具有应变。