公开(公告)号：US5418752A

公开(公告)日：1995-05-23

申请号：US963851

申请日：1992-10-20

申请人： Eliyahou Harari ,  Robert D. Norman ,  Sanjay Mehrotra

发明人： Eliyahou Harari ,  Robert D. Norman ,  Sanjay Mehrotra

IPC分类号： G11C16/02 ,  G06F3/06 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/12 ,  G06F12/16 ,  G11C5/00 ,  G11C8/02 ,  G11C8/12 ,  G11C11/56 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  G11C29/26 ,  G11C29/34 ,  G11C29/52 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C29/26 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0875 ,  G06F12/123 ,  G06F3/0601 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F3/068 ,  G06F3/0688 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/52 ,  G11C29/765 ,  G11C29/82 ,  G11C7/1039 ,  G11C8/12 ,  G06F11/1068 ,  G06F2003/0694 ,  G06F2212/2022 ,  G06F2212/312 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C2211/5621 ,  G11C2211/5634 ,  G11C2211/5643 ,  G11C2216/18 ,  G11C29/00 ,  G11C29/34

摘要： A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

摘要翻译： 具有控制电路的闪存EEprom存储器芯片的系统用作诸如由磁盘驱动器提供的非易失性存储器。 改进包括选择性多扇区擦除，其中Flash扇区的任何组合可以一起被擦除。 所选组合中的选择扇区也可以在擦除操作期间被取消选择。 另一个改进是使用替代细胞重新映射和替换有缺陷的细胞的能力。 一旦检测到有缺陷的单元，就会自动执行重新映射。 当Flash扇区的缺陷数量变大时，整个扇区被重新映射。 另一个改进是使用写高速缓存来减少写入闪存EEPROM存储器的数量，从而最小化对器件进行过多写/擦循环的应力。

公开(公告)号：US5070032A

公开(公告)日：1991-12-03

申请号：US323779

申请日：1989-03-15

申请人： Jack H. Yuan ,  Eliyahou Harari

发明人： Jack H. Yuan ,  Eliyahou Harari

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11517

摘要： An improved electrically erasable and programmable read only memory (EEprom) structure and processes of making it which results in a denser integrated circuit, improved operation and extended lifetime. In order to eliminate certain ill effects resulting from tolerances which must be allowed for registration of masks used in successive steps in forming the semiconductor structures, spacers are formed with reference to the position of existing elements in order to form floating gates and define small areas of these gates where, in a controlled fashion, a tunnel erase dielectric is formed. Alternatively, a polysilicon strip conductor is separated into separate control gates by a series of etching steps that includes an anisotropic etch of boundary oxide layers to define the area of the control gates that are coupled to the erase gate through an erase dielectric. In either case, the polysilicon layer strip can alternatively be separated by growing oxide thereon until it is completely consumed. A technique for forming a pure oxide dielectric layer of uniform thickness includes depositing a thin layer of an undoped polysilicon material and then oxidizing its surface until substantially the entire undoped polysilicon layer is consumed and made part of the resulting oxide layer. Overlapping doped regions are provided in the substrate by an ion implantation mask that adds spacers to the mask aperture to change its size between implants.

公开(公告)号：US4933739A

公开(公告)日：1990-06-12

申请号：US185699

申请日：1988-04-26

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： H01L21/822 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11

CPC分类号： H01L27/1112 ,  H01L27/11 ,  Y10S257/904

摘要： A vertical trench etched several microns deep into the silicon extending into a buried diffusion region is used to confine a vertical interconnect element. This element can be a high resistivity undoped polycrystalline silicon load resistor, a medium resistivity doped polycrystalline silicon load resistor, or a low resistivity interconnect to the buried diffusion region. This new structure can be used in compact and scalable MOS and bipolar inverters and in bistable memory storage cells.

摘要翻译： 用于限制垂直互连元件的延伸进入埋入扩散区域的硅深几微米深的垂直沟槽。 该元件可以是高电阻率未掺杂的多晶硅负载电阻器，中等电阻率掺杂的多晶硅负载电阻器或者与埋入扩散区域的低电阻率互连。 这种新结构可用于紧凑型和可扩展的MOS和双极型逆变器以及双稳态存储器单元。

公开(公告)号：US4417325A

公开(公告)日：1983-11-22

申请号：US282882

申请日：1981-07-13

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： G11C11/405 ,  G11C11/56 ,  H01L23/556 ,  H01L27/085 ,  H01L27/108 ,  H01L27/115 ,  G11C11/40 ,  B05D5/12 ,  H01L29/78 ,  H01L29/80

CPC分类号： H01L27/115 ,  G11C11/405 ,  G11C11/4125 ,  G11C11/565 ,  H01L23/556 ,  H01L27/085 ,  H01L27/108 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A memory cell comprises a substrate of a first conductivity type (preferably N type) in which is formed a first region of opposite conductivity type. Second, third and fourth regions of first conductivity type are then formed in the first region, said second and third regions being separated by a first portion of the first region and said third and fourth regions being separated by a second portion of the first region. A fifth region of first conductivity type is then formed in the second portion of the first region and a first electrode is attached to the fifth region. This electrode is electrically isolated from the second, third and fourth regions and extends on insulation over the first portion of said first region to said second region and also extends over said third region and a part of the second portion of said first region. This electrode is covered by insulation. A word line is then formed over the insulation on the first electrode so as to overlie the first electrode and together with the first electrode forms a dual electrode. The dual electrode structure forms a read transistor with channel length measured by the extent of the first portion between said second region and said third region and a write transistor with channel length measured by the separation between said third region and said fifth region, and a storage junction formed between said fifth region and said first region. By varying the voltage on the third region during the driving of the word line to either a positive or negative voltage, the charge on the first electrode is varied thereby varying the threshold voltage of the read transistor as seen by the word line. A plurality of memory cells such as described can be used to form an array and by varying either the capacitive coupling between the word line or third region and the first electrode in a selected memory cell or, alternatively, by varying the voltage applied to the third region during the writing on said first electrode of stored charge, this particular cell can be used as a reference cell during the read operation.

公开(公告)号：US4409723A

公开(公告)日：1983-10-18

申请号：US184739

申请日：1980-09-08

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： H01L27/112 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/06 ,  H01L29/788 ,  H01L29/792 ,  H01L21/283 ,  H01L21/31

CPC分类号： G11C16/0425 ,  H01L29/0638 ,  H01L29/7885

摘要： The floating gate in an N channel EPROM cell extends over the drain diffusion and over a portion of the channel thereby to form a "drain" capacitance between the drain and the floating gate and a "channel" capacitance between the channel and the floating gate. A control gate overlaps the floating gate and extends over the remainder of the channel near the source diffusion thereby to form a "control" capacitance between the channel and the control gate. These three capacitances form the coupling for driving each cell. The inversion region in the channel directly under the control gate is established directly by a "write or read access" voltage applied to the control gate. The inversion region in the channel directly under the floating gate is established indirectly through the drain and control capacitances and the channel capacitance by the control gate voltage and by another write access voltage applied to the drain. In effect, the drain voltage is coupled to the portion of the channel adjacent to the drain through the series driving circuit formed by the drain capacitance and the channel capacitance. During write, hot electrons from the write channel current are directed toward and injected into the floating gate by the transverse electric field between the floating gate and the underlying channel. Stored injection charge on the floating gate raises the conduction threshold of the programmed cell, causing the cell to remain nonconductive during read when standard ("low") access voltages are applied to the control gate. An unprogrammed cell conducts in response to the low read voltages applied to its control gate and drain drive circuit. A cell is erased either by ultraviolet illumination or by electrons from the floating gate tunneling through a region of thinned oxide. The non-symmetrical arrangement of the control gate and floating gate with respect to source and drain allows a very dense array implementation.

公开(公告)号：US4072976A

公开(公告)日：1978-02-07

申请号：US754932

申请日：1976-12-28

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： H01L27/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/4232 ,  H01L27/0251 ,  H01L29/78 ,  H01L29/94 ,  Y10S148/055

摘要： The specification describes an integrated device for the input protection of MOS circuits. It consists of an MOS capacitor formed by the thinning of a section of the input gate dielectric, SiO.sub.2, and the thinning of an adjoining section of the gate metal, Al. An incoming pulse of static charge with high amplitude and short duration will break down the thinned dielectric of the capacitor before breaking down the relatively thick portion of the gate dielectric. Since the metal over the thin dielectric is also relatively thin, it evaporates from the vicinity of the fault by the generated Joule heat immediately following the breakdown. Thus, the breakdown is self healed and can be repeated many times without damaging the circuit.

摘要翻译： 该规范描述了用于MOS电路的输入保护的集成器件。 它由通过输入栅极电介质的一部分薄化而形成的MOS电容器，以及栅极金属Al的邻接部分的薄化。 具有高幅度和短持续时间的静电荷的输入脉冲将在分解栅极电介质的较厚部分之前分解电容器的变薄的电介质。 由于薄电介质上的金属也相对较薄，所以在故障附近之后立即从故障附近由产生的焦耳热蒸发掉。 因此，故障是自我愈合的，并且可以重复多次而不损坏电路。

公开(公告)号：US07858472B2

公开(公告)日：2010-12-28

申请号：US11689775

申请日：2007-03-22

申请人： Jack H. Yuan ,  Eliyahou Harari ,  Yupin K. Fong ,  George Samachisa

发明人： Jack H. Yuan ,  Eliyahou Harari ,  Yupin K. Fong ,  George Samachisa

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11548 ,  H01L29/42328 ,  H01L29/7887

摘要： An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate. Other techniques increase the thickness of dielectric between control gates in order to decrease the field coupling between them.

摘要翻译： 通过首先在半导体衬底表面上生长薄的电介质层，然后在该电介质层上沉积诸如掺杂多晶硅的导电材料层，然后将导电材料分离成行和列，形成集成的非易失性存储器电路 个别浮动门。 衬底中的电荷源和漏极扩散在整个行中连续延伸。 沉积在浮动栅极行之间的场电介质在行之间提供电隔离。 可以在行之间包括浅沟槽，而不会中断沿其长度的扩散的导电性。 在阵列和外围电路之间的衬底中形成深电介质填充沟槽作为电隔离。 包括增加浮动栅极和控制栅极之间的场耦合区域的各种技术。 其他技术增加了控制栅之间的电介质厚度，以减小它们之间的场耦合。

公开(公告)号：US20100169561A1

公开(公告)日：2010-07-01

申请号：US12724286

申请日：2010-03-15

申请人： Eliyahou Harari ,  Daniel C. Guterman ,  Robert F. Wallace

发明人： Eliyahou Harari ,  Daniel C. Guterman ,  Robert F. Wallace

IPC分类号： G06F13/12 ,  G06F12/02 ,  G06F13/00

CPC分类号： G06F13/4068 ,  G06K19/07741 ,  H05K5/0265 ,  H05K5/0282

摘要： A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.

公开(公告)号：US20100155784A1

公开(公告)日：2010-06-24

申请号：US12344022

申请日：2008-12-24

申请人： Roy E. Scheuerlein ,  Eliyahou Harari

发明人： Roy E. Scheuerlein ,  Eliyahou Harari

IPC分类号： H01L29/00 ,  H01L21/00

CPC分类号： G11C13/0007 ,  G11C13/0004 ,  G11C13/0011 ,  G11C17/16 ,  G11C2213/19 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/35 ,  G11C2213/52 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/1675

摘要： A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.

摘要翻译： 公开了一种三维非易失性存储器系统，其包括利用用于存储单元形成的共享柱结构的存储器阵列。 共享支柱结构包括两个非易失性存储元件。 每个柱的第一端表面与第一组阵列线接触一个阵列线，并且每个柱的第二端表面与第二组阵列线接触两个阵列线，所述第二组阵列线与第一组阵列线垂直分离。 每个支柱包括被分成用于支柱中的各个存储元件的部分的第一子层子集。 每个柱包括在形成在柱中的两个非易失性存储元件之间共享的层的第二子集。 各个存储元件各自包括转向元件和状态改变元件。

公开(公告)号：US20100023800A1

公开(公告)日：2010-01-28

申请号：US12539417

申请日：2009-08-11

申请人： Eliyahou Harari ,  Richard R. Heye ,  Robert D. Selinger ,  Menahem Lasser

发明人： Eliyahou Harari ,  Richard R. Heye ,  Robert D. Selinger ,  Menahem Lasser

IPC分类号： H03M13/03 ,  G06F11/07 ,  G06F11/10 ,  G06F12/02 ,  G06F12/14

CPC分类号： G06F12/0246 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2212/7201 ,  G11C16/04 ,  G11C16/0483

摘要： A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed.

摘要翻译： 公开了一种用于在主机设备和在闪存芯片上制造的闪存设备（例如，NAND闪存设备）之间进行接口的NAND控制器。 在一些实施例中，本公开的NAND控制器包括制造在控制器管芯上的电子电路，控制器管芯与闪存管芯不同，第一接口（例如，主机型接口，例如，NAND接口），用于在 电子电路和闪存设备，以及用于在控制器和主机设备之间进行接口的第二接口（例如，闪存型接口），其中第二接口是NAND接口。 根据一些实施例，第一接口是管芯间接口。 根据一些实施例，第一接口是NAND接口。 还公开了包括当前公开的NAND控制器的系统。 还公开了用于组装上述系统以及用于使用NAND控制器读取和写入数据的方法。