公开(公告)号：US20100051972A1

公开(公告)日：2010-03-04

申请号：US12535525

申请日：2009-08-04

申请人： Ding-Yuan Chen ,  Wen-Chih Chiou ,  Chen-Hua Yu

发明人： Ding-Yuan Chen ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC分类号： H01L33/00

CPC分类号： H01L25/0753 ,  H01L33/642 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/0206 ,  H05K1/113 ,  H05K2201/10106 ,  H01L2924/00014 ,  H01L2924/00

摘要： A circuit structure includes a carrier substrate, which includes a first through-via and a second through-via. Each of the first through-via and the second through-via extends from a first surface of the carrier substrate to a second surface of the carrier substrate opposite the first surface. The circuit structure further includes a light-emitting diode (LED) chip bonded onto the first surface of the carrier substrate. The LED chip includes a first electrode and a second electrode connected to the first through-via and the second through-via, respectively.

摘要翻译： 电路结构包括载体基板，其包括第一通孔和第二通孔。 第一通孔和第二通孔中的每一个从载体衬底的第一表面延伸到与第一表面相对的载体衬底的第二表面。 电路结构还包括结合到载体基板的第一表面上的发光二极管（LED）芯片。 LED芯片包括分别连接到第一通孔和第二通孔的第一电极和第二电极。

公开(公告)号：US20100032696A1

公开(公告)日：2010-02-11

申请号：US12189635

申请日：2008-08-11

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu ,  Hung-Ta Lin

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu ,  Hung-Ta Lin

IPC分类号： H01L33/00

CPC分类号： H01L33/22 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32

摘要： A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions.

摘要翻译： 提供了一种发光二极管（LED）装置。 LED装置已经凸起形成在基板上的半导体区域。 在凸起的半导体区域上形成LED结构，使得LED器件的底部接触层和有源层是保形层。 顶部接触层具有平坦的表面。 在一个实施例中，顶部接触层在多个凸起的半导体区域上是连续的，而底部接触层和有源层在相邻凸起的半导体区域之间是不连续的。

公开(公告)号：US20100009518A1

公开(公告)日：2010-01-14

申请号：US12170494

申请日：2008-07-10

申请人： Weng-Jin Wu ,  Ku-Feng Yang ,  Jung-Chih Hu ,  Wen-Chih Chiou ,  Chen-Hua Yu

发明人： Weng-Jin Wu ,  Ku-Feng Yang ,  Jung-Chih Hu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC分类号： H01L21/00

CPC分类号： H01L21/78

摘要： A method for singulating semiconductor wafers is disclosed. A preferred embodiment comprises forming scrub lines on one side of the wafer and filling the scrub lines with a temporary fill material. The wafer is then thinned by removing material from the opposite side of the wafer from the scrub lines, thereby exposing the temporary fill material on the opposite side. The temporary fill material is then removed, and the individual die are removed from the wafer.

摘要翻译： 公开了一种用于分离半导体晶片的方法。 优选的实施方案包括在晶片的一侧上形成擦洗线，并用临时填充材料填充擦洗线。 然后通过从磨擦线从晶片的相对侧移除材料来使晶片变薄，从而在相对侧上暴露临时填充材料。 然后移除临时填充材料，并且将单个模具从晶片上移除。

公开(公告)号：US20090283871A1

公开(公告)日：2009-11-19

申请号：US12178021

申请日：2008-07-23

申请人： Hung-Pin Chang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

发明人： Hung-Pin Chang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L23/538

CPC分类号： H01L25/0657 ,  H01L21/768 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

摘要翻译： 本发明提供一种制造用于半导体衬底叠层系统的半导体衬底结构的方法。 该方法包括半导体衬底，其包括前表面，背面，体层，互连层，其包括夹在导电层之间的多个金属间介电层，位于体层和互连之间的接触层 层，以及从本体层和接触层之间开始并终止于衬底背面的TSV结构。 TSV结构电耦合到互连层，并且TSV结构电耦合到背面的接合焊盘。

公开(公告)号：US20090272975A1

公开(公告)日：2009-11-05

申请号：US12189558

申请日：2008-08-11

申请人： Ding-Yuan Chen ,  Wen-Chih Chiou ,  Chia-Lin Yu ,  Chen-Hua Yu

发明人： Ding-Yuan Chen ,  Wen-Chih Chiou ,  Chia-Lin Yu ,  Chen-Hua Yu

IPC分类号： H01L33/00

CPC分类号： H01L33/007 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02595

摘要： A structure and method for a light-emitting diode are presented. A preferred embodiment comprises a substrate with a conductive, poly-crystalline, silicon-containing layer over the substrate. A first contact layer is epitaxially grown, using the conductive, poly-crystalline, silicon-containing layer as a nucleation layer. An active layer is formed over the first contact layer, and a second contact layer is formed over the active layer.

摘要翻译： 提出了一种发光二极管的结构和方法。 优选的实施方案包括在衬底上具有导电的，多晶的含硅层的衬底。 使用导电多晶硅层作为成核层，外延生长第一接触层。 在第一接触层上形成有源层，并且在有源层上形成第二接触层。

公开(公告)号：US20090008794A1

公开(公告)日：2009-01-08

申请号：US11773171

申请日：2007-07-03

申请人： Weng-Jin Wu ,  Ku-Feng Yang ,  Hung-Pin Chang ,  Wen-Chih Chiou ,  Chen-Hua Yu

发明人： Weng-Jin Wu ,  Ku-Feng Yang ,  Hung-Pin Chang ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC分类号： H01L21/66 ,  B24B7/00 ,  H01L23/48 ,  H01L21/00

CPC分类号： B24B7/228 ,  B24B37/013 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set.

摘要翻译： 公开了一种包括从半导体器件的背面研磨衬底材料的晶片减薄系统和方法。 在研磨装置中检测到电流变化，响应于第一组器件结构暴露于基底材料，其中根据检测到的电流变化停止研磨。 抛光修复表面，并继续去除额外量的基材。 监测一个或多个另外的一组装置结构穿过基底材料的曝光，以确定要除去的基底材料的附加量，其中附加的器件结构组位于半导体器件中在与第一组不同的已知深度处。

公开(公告)号：US20090001598A1

公开(公告)日：2009-01-01

申请号：US11769559

申请日：2007-06-27

申请人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

发明人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

摘要： The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.

摘要翻译： 描述了在集成电路（IC）管芯或晶片中形成通孔硅通孔（TSV），其中在接触或金属化处理之前的集成工艺中形成TSV。 然后可以在TSV已经就位之后制造触点和接合焊盘，这允许TSV更致密并且允许TSV设计中的更多自由度。 通过在TSV和接合焊盘之间提供更密集的连接，单个晶片和管芯可以直接接合在接合焊盘处。 因此，导电接合材料通过接合焊盘保持与TSV和其它IC部件的电连接。

公开(公告)号：US20080124845A1

公开(公告)日：2008-05-29

申请号：US11563973

申请日：2006-11-28

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Jean Wang

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Jean Wang

IPC分类号： H01L21/335

CPC分类号： H01L21/76898 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/14051 ,  H01L2224/14135 ,  H01L2224/14155 ,  H01L2224/14179 ,  H01L2224/17517 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29035 ,  H01L2224/29075 ,  H01L2224/29116 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/29169 ,  H01L2224/29184 ,  H01L2224/29186 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81193 ,  H01L2224/83193 ,  H01L2224/9202 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12041 ,  H01L2924/14 ,  Y10S438/926 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/049 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor gate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure; forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure; bonding the first substrate with a second substrate; removing at least a portion of the first dummy structure, thereby forming a first opening; and forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.

摘要翻译： 一种方法包括：在第一衬底和第一衬底内的至少一个第一虚拟结构之上形成晶体管栅极; 在所述栅极晶体管上形成层间电介质层（ILD）层，所述ILD层包括形成在其中的至少一个接触结构，并与所述晶体管栅极形成电接触;以及至少一个第一导电结构，其至少部分地形成在所述虚拟 结构体; 在所述ILD层上形成钝化层，所述钝化层包括形成在其中并与所述导电结构电接触的至少一个第一焊盘结构; 用第二衬底接合第一衬底; 去除所述第一虚设结构的至少一部分，从而形成第一开口; 以及在所述第一开口内形成导电材料以形成第二导电结构，所述第二导电结构电耦合到所述第一导电结构。

公开(公告)号：US20060079154A1

公开(公告)日：2006-04-13

申请号：US10964145

申请日：2004-10-12

申请人： Wen-Chih Chiou ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Wen-Chih Chiou ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： B24B7/30 ,  B24B1/00

CPC分类号： H01L21/3212 ,  B24B37/042

摘要： A chemical-mechanical polishing (CMP) process for the manufacturing of semiconductor devices is disclosed. The process includes removing a first portion of a first layer of interconnect materials using a first platen and a first slurry, removing a second portion of the first layer using a second platen and a second slurry, removing a first portion of a second layer of the interconnect materials using a second platen and a third slurry, and removing a second portion of the second layer using a third platen and a fourth slurry.

摘要翻译： 公开了用于制造半导体器件的化学机械抛光（CMP）工艺。 该方法包括使用第一压板和第一浆料去除第一层互连材料的第一部分，使用第二压板和第二浆料除去第一层的第二部分，去除第二层的第一部分 使用第二压板和第三浆料的互连材料，以及使用第三压板和第四浆料除去第二层的第二部分。

公开(公告)号：US08803189B2

公开(公告)日：2014-08-12

申请号：US12538701

申请日：2009-08-10

申请人： Chen-Hua Yu ,  Chia-Lin Yu ,  Ding-Yuan Chen ,  Wen-Chih Chiou ,  Hung-Ta Lin

发明人： Chen-Hua Yu ,  Chia-Lin Yu ,  Ding-Yuan Chen ,  Wen-Chih Chiou ,  Hung-Ta Lin

IPC分类号： H01L33/00

CPC分类号： H01L21/8258 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02642 ,  H01L21/02645 ,  H01L29/2003 ,  H01L29/66462 ,  H01L33/007

摘要： A circuit structure includes a substrate; a patterned mask layer over the substrate, wherein the patterned mask layer includes a plurality of gaps; and a group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layer includes a first portion over the mask layer and second portions in the gaps, wherein the III-V compound semiconductor layer overlies a buffer/nucleation layer.

摘要翻译： 电路结构包括基板; 在所述衬底上的图案化掩模层，其中所述图案化掩模层包括多个间隙; 和III族V族（III-V）族化合物半导体层。 III-V族化合物半导体层包括掩模层上的第一部分和间隙中的第二部分，其中III-V族化合物半导体层覆盖缓冲层/成核层。