公开(公告)号：US20150004451A1

公开(公告)日：2015-01-01

申请号：US14311489

申请日：2014-06-23

Applicant: Infineon Technologies AG

Inventor： Klaus Elian ,  Jochen Dangelmaier ,  Manfred Fries ,  Juergen Hoegerl ,  Georg Meyer-Berg ,  Thomas Mueller ,  Guenther Ruhl ,  Horst Theuss ,  Mathias Vaupel

IPC: G01R31/36 ,  H01M10/48

CPC classification number: H01M10/48 ,  G01R31/3689 ,  H01M6/505 ,  H01M10/488

Abstract: An apparatus for determining a state of a rechargeable battery or of a battery has a sensor device and an evaluation device. The sensor device brings about an interaction between an optical signal and a part of the rechargeable battery or of the battery, which part indicates optically acquirable information about a state of the rechargeable battery or of the battery, and detects an optical signal caused by the interaction. The sensor device furthermore provides a detection signal having information about the detected optical signal. The evaluation device determines information about a state of the rechargeable battery or of the battery on the basis of the information of the detection signal. Furthermore, the evaluation device provides a state signal having the information about the determined state.

Abstract translation: 用于确定可再充电电池或电池的状态的装置具有传感器装置和评估装置。 该传感器装置引起光信号与可再充电电池或电池的一部分之间的相互作用，该部分指示关于可再充电电池或电池的状态的光学上可获取的信息，并检测由相互作用引起的光信号 。 传感器装置还提供具有关于检测到的光信号的信息的检测信号。 评估装置基于检测信号的信息来确定关于可再充电电池或电池的状态的信息。 此外，评估装置提供具有关于所确定的状态的信息的状态信号。

公开(公告)号：US08896128B2

公开(公告)日：2014-11-25

申请号：US13678675

申请日：2012-11-16

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Georg Meyer-Berg

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3171 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is provided, the integrated circuit including: a chip having a first chip side and a second chip side opposite to the first chip side, the chip having at least one contact area on the second chip side; encapsulation material at least partially covering the chip; and at least one contact via comprising electrical conductive material contacting the at least one contact area and extending through the encapsulation material and through the chip between the first chip side and the second chip side.

Abstract translation: 提供一种集成电路，所述集成电路包括：具有第一芯片侧和与所述第一芯片侧相对的第二芯片侧的芯片，所述芯片在所述第二芯片侧具有至少一个接触区域; 封装材料至少部分覆盖芯片; 以及至少一个接触通孔，其包括与所述至少一个接触区域接触并延伸穿过所述封装材料并通过所述芯片在所述第一芯片侧和所述第二芯片侧之间的导电材料。

公开(公告)号：US20140264950A1

公开(公告)日：2014-09-18

申请号：US13798141

申请日：2013-03-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Rainer Steiner ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg ,  Joachim Mahler

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/24246 ,  H01L2224/2518 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/07802 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.

Abstract translation: 在各种实施例中，提供了芯片布置。 芯片布置可以包括芯片载体和安装在芯片载体上的芯片。 芯片可以包括至少两个芯片触点和芯片与芯片载体之间的绝缘粘合剂，以将芯片粘附到芯片载体上。 所述至少两个芯片触点可以电耦合到芯片载体。

公开(公告)号：US20190287907A1

公开(公告)日：2019-09-19

申请号：US16279370

申请日：2019-02-19

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Georg Meyer-Berg ,  Guenter Tutsch

IPC: H01L23/532 ,  H01L23/31 ,  H01L23/495 ,  H01L25/07 ,  H01L23/00 ,  H01L21/56

Abstract: A package and method of manufacturing a package is disclosed. In one example, the package includes an electronic chip and a dielectric structure comprising a highly filled cross-linked thermoplastic material.

公开(公告)号：US20190221521A1

公开(公告)日：2019-07-18

申请号：US16249172

申请日：2019-01-16

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier ,  Georg Meyer-Berg

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/00 ,  H01L24/25 ,  H01L25/00

Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

公开(公告)号：US10297564B2

公开(公告)日：2019-05-21

申请号：US15725796

申请日：2017-10-05

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Georg Meyer-Berg

IPC: C09J5/06 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  C09J163/00 ,  C09J177/04 ,  C09J179/02 ,  C09J181/00 ,  C09J183/04

Abstract: A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.

公开(公告)号：US20180350683A1

公开(公告)日：2018-12-06

申请号：US16102174

申请日：2018-08-13

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Claus von Waechter ,  Michael Bauer ,  Holger Doepke ,  Dominic Maier ,  Daniel Porwol ,  Tobias Schmidt

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  B32B37/26

Abstract: A method for handling a product substrate includes bonding a carrier to the product substrate by: applying a layer of a temporary adhesive having a first coefficient of thermal expansion onto a surface of the carrier; and bonding the carrier to the product substrate using the applied temporary adhesive. A surface of the temporary adhesive is in direct contact to a surface of the product substrate. The temporary adhesive includes or is adjacent a filler material having a second coefficient of thermal expansion which is smaller than the first coefficient of thermal expansion, so that stress occurs inside the temporary adhesive layer or at an interface to the product substrate or the carrier during cooling down of the temporary adhesive layer.

公开(公告)号：US20170170082A1

公开(公告)日：2017-06-15

申请号：US15442084

申请日：2017-02-24

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall ,  Michael Goroll ,  Rainer Dudek

IPC: H01L23/04 ,  H01L25/10 ,  H05K1/18

CPC classification number: H01L23/04 ,  G06F17/5068 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49811 ,  H01L24/81 ,  H01L25/10 ,  H01L2224/01 ,  H01L2224/291 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/83447 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/35121 ,  H05K1/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package includes a block having opposing first and second main surfaces and sides between the first and second main surfaces, and an encapsulation material at least partly covering the block. One or both of the main surfaces of the block has recessed regions. The recessed regions do not extend completely through the block from one main surface to the other main surface. The encapsulation material fills the recessed regions to form an interlocked connection between the block and the encapsulation material. Additional semiconductor package embodiments are provided.

公开(公告)号：US09576867B2

公开(公告)日：2017-02-21

申请号：US15093528

申请日：2016-04-07

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall

IPC: H01L23/48 ,  H01L21/66 ,  G01R31/26 ,  G01R31/28 ,  H01L23/58 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L23/525

CPC classification number: H01L22/32 ,  G01R31/26 ,  G01R31/28 ,  G01R31/2853 ,  G01R31/2884 ,  H01L21/7685 ,  H01L21/76868 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53204 ,  H01L23/58 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05556 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.

Abstract translation: 公开了包括延展层的装置，用于制造包括延展层的部件的方法和用于测试部件的方法。 实施例包括在第一导电层和延性层之间包括第一导电层，延性层和脆性层的电子器件。

公开(公告)号：US20160218039A1

公开(公告)日：2016-07-28

申请号：US15002009

申请日：2016-01-20

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Claus von Waechter ,  Michael Bauer ,  Holger Doepke ,  Dominic Maier ,  Daniel Porwol ,  Tobias Schmidt

IPC: H01L21/78 ,  H05K3/00 ,  H01L21/683

CPC classification number: H01L21/78 ,  B32B37/26 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/562 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  H05K3/007 ,  Y10S156/93 ,  Y10S156/941

Abstract: A method for handling a product substrate includes bonding a carrier to the product substrate. A layer of a permanent adhesive is applied onto a surface of the carrier. A structured intermediate layer is provided. The applied permanent adhesive bonds the carrier to the product substrate. The structured intermediate layer is arranged between the product substrate and the carrier. A surface of the structured intermediate layer and a surface of the permanent adhesive are in direct contact to a surface of the product substrate. The structured intermediate layer decreases a bonding strength between the product substrate and the carrier.

Abstract translation: 一种用于处理产品基板的方法包括将载体接合到产品基板。 将一层永久性粘合剂施加到载体的表面上。 提供了结构化的中间层。 施加的永久性粘合剂将载体粘合到产品基材上。 结构化中间层布置在产品基板和载体之间。 结构化中间层的表面和永久性粘合剂的表面直接接触产品基材的表面。 结构化中间层降低了产品基板和载体之间的结合强度。