公开(公告)号：US09324652B2

公开(公告)日：2016-04-26

申请号：US14630572

申请日：2015-02-24

申请人： INTEL CORPORATION

发明人： Manish Chandhok ,  Hui Jae Yoo ,  Yan A. Borodovsky ,  Florian Gstrein ,  David N. Shykind ,  Kevin L. Lin

IPC分类号： H01L21/336 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L21/3213 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.

摘要翻译： 一种方法，包括将互连材料的厚度尺寸图案化为具有从布线延伸的一个或多个通孔的布线的厚度尺寸，并将介电材料引入到互连材料上。 一种包括将互连材料沉积和图案化成布线和一个或多个通孔的方法; 以及在所述互连材料上引入介电材料，使得所述一个或多个通孔通过所述介电材料暴露。 一种装置，包括在第一平面中的第一互连层和在衬底上的第二平面中的第二互连; 以及分离所述第一和第二互连层的电介质层，其中所述第一互连层包括包括布线和至少一个通孔的整体，所述至少一个通孔从所述布线延伸到所述第二互连层的布线。

公开(公告)号：US12037434B2

公开(公告)日：2024-07-16

申请号：US17313932

申请日：2021-05-06

申请人： Intel Corporation

发明人： Eungnak Han ,  Gurpreet Singh ,  Tayseer Mahdi ,  Florian Gstrein ,  Lauren Doyle ,  Marie Krysak ,  James Blackwell ,  Robert Bristol

IPC分类号： C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/522 ,  H01L23/528

CPC分类号： C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

摘要： A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

公开(公告)号：US20240203868A1

公开(公告)日：2024-06-20

申请号：US18066301

申请日：2022-12-15

申请人： Intel Corporation

发明人： Gurpreet Singh ,  Manish Chandhok ,  David Nathan Shykind ,  Richard E. Schenker ,  Florian Gstrein ,  Eungnak Han ,  Nafees Aminul Kabir ,  Sean Michael Pursel ,  Nityan Labros Nair ,  Robert Seidel

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76879

摘要： Metal lines are formed through serial DSA processes. A first DSA process may define a pattern of first hard masks. First metal lines are fabricated based on the first hard masks. A metal cut crossing one or more first metal lines may be formed. A width of the metal cut is no greater than a pitch of the first metal lines. After the metal cut is formed, a second DSA process is performed to define a pattern of second hard masks. Edges of a second hard mask may align with edges of a first metal line. An insulator may be formed around a second hard mask to form an insulative structure. An axis of the insulative structure may be aligned with an axis of a first metal line. Second metal lines are formed based on the second hard masks and have a greater height than the first metal lines.

公开(公告)号：US20240194672A1

公开(公告)日：2024-06-13

申请号：US18064362

申请日：2022-12-12

申请人： Intel Corporation

发明人： Bharath Bangalore Rajeeva ,  Manish Chandhok ,  Gurpreet Singh ,  Kevin Huggins ,  Eungnak Han ,  Florian Gstrein ,  Marko Radosavljevic

IPC分类号： H01L27/088 ,  H01L21/02 ,  H01L21/027 ,  H01L23/522 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0271 ,  H01L23/5226 ,  H01L29/1033 ,  H01L29/42364

摘要： An IC device may include a first conductive structure in a first section and a second conductive structure in a second section. The second conductive structure is in parallel with the first conductive structure in a first direction. A dimension of the second conductive structure in a second direction perpendicular to the first direction is greater than a dimension of the first conductive structure in the second direction. The first conductive structure may be coupled to a channel region of a transistor. The second conductive structure may be coupled to a channel region of another transistor. A first structure comprising a first dielectric material may be over the first conductive structure. A second structure comprising a second dielectric material may be over the second section. A third structure comprising the first dielectric material may be over the second conductive structure and be at least partially surrounded by the second structure.

公开(公告)号：US11984317B2

公开(公告)日：2024-05-14

申请号：US17308813

申请日：2021-05-05

申请人： Intel Corporation

发明人： Marie Krysak ,  James Blackwell ,  Lauren Doyle ,  Brian Zaccheo ,  Patrick Theofanis ,  Michael Robinson ,  Florian Gstrein

IPC分类号： H01L21/027 ,  G03F7/004 ,  G03F7/20 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/0274 ,  G03F7/0042 ,  H01L21/76877 ,  H01L23/5226 ,  G03F7/2004

摘要： Techniques, structures, and materials related to extreme ultraviolet (EUV) lithography are discussed. Multiple patterning inclusive of first patterning a grating of parallel lines and second patterning utilizing EUV lithography to form plugs in the grating, and optional trimming of the plugs may be employed. EUV resists, surface treatments, resist additives, and optional processing inclusive of plug healing, angled etch processing, electric field enhanced post exposure bake are described, which provide improved processing reliability, feature definition, and critical dimensions.

公开(公告)号：US11955343B2

公开(公告)日：2024-04-09

申请号：US17701367

申请日：2022-03-22

申请人： Intel Corporation

发明人： Robert L. Bristol ,  Marie Krysak ,  James M. Blackwell ,  Florian Gstrein ,  Kent N. Frasure

IPC分类号： G03F7/039 ,  G03F7/004 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/31144 ,  G03F7/0045 ,  G03F7/0392 ,  G03F7/203 ,  G03F7/38 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76816

摘要： Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

公开(公告)号：US11373950B2

公开(公告)日：2022-06-28

申请号：US17110215

申请日：2020-12-02

申请人： Intel Corporation

发明人： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

摘要： Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US11320734B2

公开(公告)日：2022-05-03

申请号：US16316594

申请日：2016-09-30

申请人： Intel Corporation

发明人： Marie Krysak ,  James M. Blackwell ,  Robert L. Bristol ,  Florian Gstrein

IPC分类号： G03F7/004 ,  G03F7/20 ,  B82Y30/00 ,  B82Y40/00

摘要： A photosensitive composition including metal nanoparticles capped with an organic ligand, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum. A method including synthesizing metal particles including a diameter of 5 nanometers or less, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum; and capping the metal particles with an organic ligand. A method including depositing a photosensitive composition on a semiconductor substrate, wherein the photosensitive composition includes metal nanoparticles capped with an organic ligand and the nanoparticles include a metal that absorbs light in the extreme ultraviolet spectrum; exposing the photosensitive composition to light in an ultraviolet spectrum through a mask including a pattern; and transferring the mask pattern to the photosensitive composition.

公开(公告)号：US11158515B2

公开(公告)日：2021-10-26

申请号：US16334324

申请日：2016-09-30

申请人： Intel Corporation

发明人： Kevin Lin ,  Rahim Kasim ,  Manish Chandhok ,  Florian Gstrein

IPC分类号： H01L21/3213 ,  H01L21/302 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

摘要： Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.

公开(公告)号：US20210143265A1

公开(公告)日：2021-05-13

申请号：US17154755

申请日：2021-01-21

申请人： Intel Corporation

发明人： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49

摘要： Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.