摘要:
Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
摘要:
Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.
摘要:
The invention is directed to unique high-surface area BEOL capacitor structures with high-k dielectric layers and methods for fabricating the same. These high-surface area BEOL capacitor structures may be used in analog and mixed signal applications. The capacitor is formed within a trench with pedestals within the trench to provide additional surface area. The top and bottom electrodes are created using damascene integration scheme. The dielectric layer is created as a multilayer dielectric film comprising for instance Al2O3, Al2O3/Ta2O5, Al2O3/Ta2O5/Al2O3 and the like. The dielectric layer may be deposited by methods like atomic layer deposition or chemical vapor deposition. The dielectric layer used in the capacitor may also be produced by anodic oxidation of a metallic precursor to yield a high dielectric constant oxide layer.
摘要翻译:本发明涉及具有高k电介质层的独特的高表面积BEOL电容器结构及其制造方法。 这些高表面积BEOL电容器结构可用于模拟和混合信号应用。 电容器形成在具有沟槽内的基座的沟槽内,以提供额外的表面积。 顶部和底部电极使用大马士革集成方案创建。 电介质层被形成为多层电介质膜,该多层电介质膜包括例如Al 2 O 3 O 3,Al 2 O 3 O 3, / Ta 2 O 5,O 2 O 3 / Ta 2 O 2, 2/3/3/3等等。 电介质层可以通过诸如原子层沉积或化学气相沉积的方法沉积。 电容器中使用的电介质层也可以通过金属前体的阳极氧化产生高介电常数氧化物层。
摘要:
A method of improving the tolerance of a back-end-of-the-line (BEOL) thin film resistor is provided. Specifically, the method of the present invention includes an anodization step which is capable of converting a portion of base resistor film into an anodized region. The anodized resistor thus formed has a sheet resistivity that is higher than that of the base resistor film.
摘要:
A method of forming patterned metallization by electrodeposition under illumination without external voltage supply on a photovoltaic structure or on n-type region of a transistor/junction.
摘要:
The present disclosure relates to an improved method of providing a Ni silicide metal contact on a silicon surface by electrodepositing a Ni film on a silicon substrate. The improved method results in a controllable silicide formation wherein the silicide has a uniform thickness. The metal contacts may be incorporated in, for example, CMOS devices, MEM (micro-electro-mechanical) devices, and photovoltaic cells.
摘要:
An electrochemical process comprising: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, said semiconductor wafer functioning as a first electrode; providing a second electrode in the electrolytic solution, the first and second electrode connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes. The invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical process.
摘要:
A filter includes a membrane having a plurality of nanochannels formed therein. A first surface charge material is deposited on an end portion of the nanochannels. The first surface charge material includes a surface charge to electrostatically influence ions in an electrolytic solution such that the nanochannels reflect ions back into the electrolytic solution while passing a fluid of the electrolytic solution. Methods for making and using the filter are also provided.
摘要:
A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.