公开(公告)号：US07446411B2

公开(公告)日：2008-11-04

申请号：US11257784

申请日：2005-10-24

Applicant: Brian W. Condie ,  Lakshminarayan Viswanathan ,  Richard W. Wetz

Inventor： Brian W. Condie ,  Lakshminarayan Viswanathan ,  Richard W. Wetz

IPC: H01L23/10

CPC classification number: H01L23/10 ,  H01L23/047 ,  H01L23/053 ,  H01L23/057 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/83 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2223/6644 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29144 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/157 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/01025 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/83205

Abstract: A semiconductor structure (100, 900) includes a substrate (110) having a surface (111) and also includes one or more semiconductor chips (120) located over the substrate surface. The semiconductor structure further includes an electrical isolator structure (340) located over the substrate surface, where the electrical isolator structure includes one or more electrical leads (341, 342) and an organic-based element (343) molded to the electrical leads. The semiconductor structure also includes a solder element (350) coupling together the electrical isolator structure and the substrate surface.

Abstract translation: 半导体结构（100,900）包括具有表面（111）的衬底（110），并且还包括位于衬底表面上方的一个或多个半导体芯片（120）。 半导体结构还包括位于衬底表面上的电隔离器结构（340），其中电隔离器结构包括一个或多个电引线（341,342）和模制到电引线的有机元件（343）。 半导体结构还包括将电隔离器结构和衬底表面耦合在一起的焊料元件（350）。

公开(公告)号：US20070090515A1

公开(公告)日：2007-04-26

申请号：US11257784

申请日：2005-10-24

Applicant: Brian Condie ,  Lakshminarayan Viswanathan ,  Richard Wetz

Inventor： Brian Condie ,  Lakshminarayan Viswanathan ,  Richard Wetz

IPC: H01L23/12

CPC classification number: H01L23/10 ,  H01L23/047 ,  H01L23/053 ,  H01L23/057 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/83 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2223/6644 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29144 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/157 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/01025 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/83205

Abstract: A semiconductor structure (100, 900) includes a substrate (110) having a surface (111) and also includes one or more semiconductor chips (120) located over the substrate surface. The semiconductor structure further includes an electrical isolator structure (340) located over the substrate surface, where the electrical isolator structure includes one or more electrical leads (341, 342) and an organic-based element (343) molded to the electrical leads. The semiconductor structure also includes a solder element (350) coupling together the electrical isolator structure and the substrate surface.

Abstract translation: 半导体结构（100,900）包括具有表面（111）的衬底（110），并且还包括位于衬底表面上方的一个或多个半导体芯片（120）。 半导体结构还包括位于衬底表面上的电隔离器结构（340），其中电隔离器结构包括一个或多个电引线（341,342）和模制到电引线的有机元件（343）。 半导体结构还包括将电隔离器结构和基板表面耦合在一起的焊料元件（350）。

公开(公告)号：US06072238A

公开(公告)日：2000-06-06

申请号：US287282

申请日：1999-04-07

Applicant: Lakshminarayan Viswanathan ,  David F. Abdo ,  Gerald R. Miller

Inventor： Lakshminarayan Viswanathan ,  David F. Abdo ,  Gerald R. Miller

IPC: H01L23/66 ,  H01L23/34

CPC classification number: H01L23/66 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2924/30111

Abstract: A semiconductor device (10) suitable for use in RF applications and a method of forming the semiconductor device (10). An RF transistor die (31) is bonded to a heatsink (21). The heatsink (21) having the semiconductor chip (31) mounted thereto is coupled to a printed circuit board (11), wherein the RF transistor die (31) extends through an opening (14) in the printed circuit board (11). Conductors (18, 19) on the printed circuit board (11) are coupled to the semiconductor chip (31) via wirebonds (35, 36).

Abstract translation: 适用于RF应用的半导体器件（10）和形成半导体器件（10）的方法。 RF晶体管管芯（31）与散热片（21）接合。 安装有半导体芯片（31）的散热器（21）耦合到印刷电路板（11），其中RF晶体管管芯（31）延伸穿过印刷电路板（11）中的开口（14）。 印刷电路板（11）上的导体（18,19）经由引线键（35,36）耦合到半导体芯片（31）。

公开(公告)号：US09312817B2

公开(公告)日：2016-04-12

申请号：US13554034

申请日：2012-07-20

Applicant: Peter H. Aaen ,  David J. Dougherty ,  Manuel F. Romero ,  Lakshminarayan Viswanathan

Inventor： Peter H. Aaen ,  David J. Dougherty ,  Manuel F. Romero ,  Lakshminarayan Viswanathan

IPC: H03F3/20 ,  H03F1/02 ,  H03F3/195 ,  H03F3/24 ,  H01L23/552 ,  H01L23/66

CPC classification number: H01L23/5227 ,  H01L23/293 ,  H01L23/49506 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6644 ,  H01L2224/49175 ,  H01L2924/3011 ,  H03F1/0288 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F3/245 ,  H01L2924/00

Abstract: A single semiconductor device package that reduces electromagnetic coupling between elements of a semiconductor device embodied within the package is provided. For a dual-path amplifier, such as a Doherty power amplifier, an isolation feature that separates carrier amplifier elements from peaking amplifier elements is included within the semiconductor device package. The isolation feature can take the form of a structure that is constructed of a conductive material coupled to ground and which separates the elements of the amplifier. The isolation feature can be included in a variety of semiconductor packages, including air cavity packages and overmolded packages. Through the use of the isolation feature provided by embodiments of the present invention a significant improvement in signal isolation between amplifier elements is realized, thereby improving performance of the dual-path amplifier.

Abstract translation: 提供了减少在封装内体现的半导体器件的元件之间的电磁耦合的单个半导体器件封装。 对于诸如Doherty功率放大器的双通道放大器，将载波放大器元件与峰值放大器元件分离的隔离特征包括在半导体器件封装内。 隔离特征可以采取由耦合到地并且分离放大器的元件的导电材料构成的结构的形式。 隔离特征可以包括在各种半导体封装中，包括气腔封装和包覆成型的封装。 通过使用由本发明的实施例提供的隔离特征，实现放大器元件之间的信号隔离的显着改进，从而提高双路放大器的性能。

公开(公告)号：US09281283B2

公开(公告)日：2016-03-08

申请号：US13611793

申请日：2012-09-12

Applicant: Lakshminarayan Viswanathan ,  Jeffrey K. Jones ,  Scott D. Marshall

Inventor： Lakshminarayan Viswanathan ,  Jeffrey K. Jones ,  Scott D. Marshall

IPC: H01L23/66 ,  H01L23/047 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L23/047 ,  H01L23/49589 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of semiconductor devices (e.g., RF devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit and/or an impedance matching circuit. Embodiments also include method of manufacturing such semiconductor devices.

Abstract translation: 半导体器件（例如，RF器件）的实施例包括衬底，隔离结构，有源器件，引线和电路。 隔离结构耦合到衬底，并且包括开口。 有源器件区域由通过开口暴露的衬底表面的一部分限定。 有源器件耦合到有源器件区域内的衬底表面。 电路电耦合在有源器件和引线之间。 电路包括位于有源器件区域外的一个或多个元件（例如，物理耦合到隔离结构和/或在引线下方）。 位于有源器件区域之外的元件可以包括封装端接电路和/或阻抗匹配电路的元件。 实施例还包括制造这种半导体器件的方法。

公开(公告)号：US20150116961A1

公开(公告)日：2015-04-30

申请号：US14066689

申请日：2013-10-30

Applicant: Lakshminarayan Viswanathan

Inventor： Lakshminarayan Viswanathan

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0256 ,  H05K2201/0769 ,  H05K2201/09781 ,  Y10T29/49117

Abstract: A circuit includes a structure for inhibiting dendrite formation. The circuit includes a first electrode disposed within a first area of the circuit, wherein the first electrode is configured to be coupled to an ionic source that forms ions when a first electric potential is applied to the first electrode. The circuit also includes a second electrode disposed within a second area of the circuit. The second electrode is configured to receive a second electric potential that is less than the first electric potential and that causes the ions to migrate toward the second electrode to contribute to dendrite formation. The circuit further includes a structure disposed within a third area of the circuit. The structure is configured to receive a third electric potential to create a barrier that inhibits the migration of at least some of the ions from the first to the second electrode to inhibit dendrite formation.

Abstract translation: 电路包括抑制枝晶形成的结构。 电路包括设置在电路的第一区域内的第一电极，其中第一电极被配置为耦合到当向第一电极施加第一电位时形成离子的离子源。 电路还包括设置在电路的第二区域内的第二电极。 第二电极被配置为接收小于第一电位的第二电位并且导致离子朝向第二电极迁移以有助于枝晶形成。 电路还包括设置在电路的第三区域内的结构。 该结构被配置为接收第三电位以产生阻挡至少一些离子从第一电极到第二电极迁移以阻止枝晶形成的屏障。

公开(公告)号：US20140332941A1

公开(公告)日：2014-11-13

申请号：US14341292

申请日：2014-07-25

Applicant: Lakshminarayan Viswanathan ,  Lakshmi N. Ramanathan ,  Audel A. Sanchez ,  Fernando A. Santos

Inventor： Lakshminarayan Viswanathan ,  Lakshmi N. Ramanathan ,  Audel A. Sanchez ,  Fernando A. Santos

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/568 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/49506 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

Abstract translation: 封装的半导体器件可以包括终端表面，其终端被配置为表面安装到印刷电路板的无引线互连。 第一凸缘具有第一表面和第二表面。 第一表面提供第一个终端，第二表面与第一表面相对。 第二凸缘还具有第一表面和第二表面，其中第一表面提供端接件中的第二表面，并且第二表面与第一表面相对。 模具通过熔点超过240℃的材料安装到第一凸缘的第二表面上。电互连件在模具与第二凸缘的与端接表面相对的第二表面之间延伸，使得电气 互连，第一凸缘和第二凸缘基本上容纳在主体内。

公开(公告)号：US08698291B2

公开(公告)日：2014-04-15

申请号：US13326636

申请日：2011-12-15

Applicant: Audel A. Sanchez ,  Fernando A. Santos ,  Lakshminarayan Viswanathan

Inventor： Audel A. Sanchez ,  Fernando A. Santos ,  Lakshminarayan Viswanathan

IPC: H01L23/02

CPC classification number: H01L21/56 ,  H01L21/76895 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/20755 ,  H01L2924/00012

Abstract: A packaged leadless semiconductor device (20) includes a heat sink flange (24) to which semiconductor dies (26) are coupled using a high temperature die attach process. The semiconductor device (20) further includes a frame structure (28) pre-formed with bent terminal pads (44). The frame structure (28) is combined with the flange (24) so that a lower surface (36) of the flange (24) and a lower section (54) of each terminal pad (44) are in coplanar alignment, and so that an upper section (52) of each terminal pad (44) overlies the flange (24). Interconnects (30) interconnect the die (26) with the upper section (52) of the terminal pad (44). An encapsulant (32) encases the frame structure (28), flange (24), die (26), and interconnects (30) with the lower section (54) of each terminal pad (44) and the lower surface (36) of the flange (24) remaining exposed from the encapsulant (32).

Abstract translation: 封装的无引线半导体器件（20）包括散热器法兰（24），半导体管芯（26）使用高温管芯附接工艺耦合到该散热器法兰（24）。 半导体器件（20）还包括预先形成有弯曲的端子焊盘（44）的框架结构（28）。 框架结构（28）与凸缘（24）组合，使得凸缘（24）的下表面（36）和每个端子垫（44）的下部（54）处于共面对准，并且因此 每个端子焊盘（44）的上部（52）覆盖在凸缘（24）上。 互连件（30）将管芯（26）与端子焊盘（44）的上部（52）互连。 密封剂（32）将框架结构（28），凸缘（24），模具（26）和互连件（30）与每个端子垫（44）的下部（54）和下表面（36） 所述凸缘（24）保持暴露于所述密封剂（32）。

公开(公告)号：US20140070397A1

公开(公告)日：2014-03-13

申请号：US13613979

申请日：2012-09-13

Applicant: Lakshminarayan Viswanathan ,  Scott M. Hayes ,  Scott D. Marshall ,  Mahesh K. Shah

Inventor： Lakshminarayan Viswanathan ,  Scott M. Hayes ,  Scott D. Marshall ,  Mahesh K. Shah

IPC: H01L21/56 ,  H01L23/34

CPC classification number: H01L24/24 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect.

Abstract translation: 提供了一种通过将具有高导热性的金属“硬币”嵌入封装基板或印刷电路板以及将功率器件裸片耦合到金属硬币上的方法和装置，用于将大功率器件管芯并入更小的系统封装中。 在一个实施例中，功率器件管芯可以附接到封装衬底或PCB中已经嵌入的金属硬币。 功率器件裸片可以直接耦合到嵌入式金属硬币，或者功率器件裸片可以附接到金属插入器，然后将其粘合到嵌入的金属硬币上。 在另一个实施例中，模具可以附接到金属硬币，然后可以组装PCB或封装基板以并入铜币。 活性芯片通过引线键合或其他无源部件彼此耦合，或者使用组合互连。

公开(公告)号：US20130320515A1

公开(公告)日：2013-12-05

申请号：US13484664

申请日：2012-05-31

Applicant: Lakshminarayan Viswanathan ,  Lakshmi N. Ramanathan ,  Audel A. Sanchez ,  Fernando A. Santos

Inventor： Lakshminarayan Viswanathan ,  Lakshmi N. Ramanathan ,  Audel A. Sanchez ,  Fernando A. Santos

IPC: H01L23/495 ,  H01L21/78 ,  H01L21/50

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/568 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/49506 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

Abstract translation: 封装的半导体器件可以包括终端表面，其终端被配置为表面安装到印刷电路板的无引线互连。 第一凸缘具有第一表面和第二表面。 第一表面提供第一个终端，第二表面与第一表面相对。 第二凸缘还具有第一表面和第二表面，其中第一表面提供端接件中的第二表面，并且第二表面与第一表面相对。 模具通过熔点超过240℃的材料安装到第一凸缘的第二表面上。电互连件在模具与第二凸缘的与端接表面相对的第二表面之间延伸，使得电气 互连，第一凸缘和第二凸缘基本上容纳在主体内。