公开(公告)号：US20220139848A1

公开(公告)日：2022-05-05

申请号：US17575789

申请日：2022-01-14

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Yi-Jou LIN

IPC: H01L23/00 ,  H01L23/053 ,  H01L23/367 ,  H01L23/31 ,  H01L25/16 ,  H01L23/498

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die.

公开(公告)号：US20200273812A1

公开(公告)日：2020-08-27

申请号：US15930645

申请日：2020-05-13

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  Yung-Chang LIEN

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/16 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a frame, a redistribution layer, and a first semiconductor die. The substrate has a wiring structure and is surrounded by a molding material. The frame is disposed in the molding material and surrounds the substrate. The redistribution layer is disposed over the substrate and electrically coupled to the wiring structure. The first semiconductor die is disposed over the redistribution layer.

公开(公告)号：US20180233452A1

公开(公告)日：2018-08-16

申请号：US15891481

申请日：2018-02-08

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  Chia-Cheng CHANG ,  I-Hsuan PENG

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5283 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package overlying a portion of the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure, a first semiconductor die and a molding compound. The first semiconductor die is disposed on a first surface of the first RDL structure and electrically coupled to the first RDL structure. The molding compound is positioned overlying the first semiconductor die and the first surface of the first RDL structure. The second semiconductor package includes a first memory die and a second memory die vertically stacked on the first memory die. The second memory die is electrically coupled to first memory die by through silicon via (TSV) interconnects formed passing through the second memory die.

公开(公告)号：US20170338175A1

公开(公告)日：2017-11-23

申请号：US15481500

申请日：2017-04-07

Applicant: MEDIATEK INC.

Inventor： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Che-Hung KUO ,  Che-Ya CHOU ,  Wei-Che HUANG

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.

公开(公告)号：US20170110406A1

公开(公告)日：2017-04-20

申请号：US15393387

申请日：2016-12-29

Applicant: MediaTek Inc.

Inventor： Ming-Tzong YANG ,  Cheng-Chou HUNG ,  Wei-Che HUANG ,  Yu-Hua HUANG ,  Tzu-Hung LIN ,  Kuei-Ti CHAN ,  Ruey-Beei WU ,  Kai-Bin WU

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2225/06544

Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.

公开(公告)号：US20170098628A1

公开(公告)日：2017-04-06

申请号：US15212125

申请日：2016-07-15

Applicant: MediaTek Inc.

Inventor： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO ,  Wei-Che HUANG

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/03011 ,  H01L2224/03502 ,  H01L2224/036 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06136 ,  H01L2224/06146 ,  H01L2224/06156 ,  H01L2224/06166 ,  H01L2224/10126 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/17136 ,  H01L2224/17146 ,  H01L2224/17156 ,  H01L2224/17166 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/214 ,  H01L2924/00

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor body and a conductive structure disposed below the semiconductor body. The semiconductor package structure also includes an insulating layer surrounding the conductive structure. The semiconductor package structure further includes a redistribution layer structure coupled to the conductive structure. In addition, the semiconductor package structure includes a molding compound surrounding the semiconductor body. A portion of the molding compound extends between the redistribution layer structure and the semiconductor body.

公开(公告)号：US20170084488A1

公开(公告)日：2017-03-23

申请号：US15365435

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou HUNG ,  Ming-Tzong YANG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG ,  Tzu-Hung LIN

IPC: H01L21/768 ,  H01L23/00 ,  H01L29/06 ,  H01L23/48 ,  H01L21/761

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.

公开(公告)号：US20170077073A1

公开(公告)日：2017-03-16

申请号：US15203418

申请日：2016-07-06

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Chi-Chin LIEN ,  Nai-Wei LIU ,  I-Hsuan PENG ,  Ching-Wen HSIAO ,  Wei-Che HUANG

IPC: H01L25/10

CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure.

Abstract translation: 提供半导体封装结构。 半导体封装结构包括第一半导体封装，其包括具有第一表面和与其相对的第二表面的第一半导体管芯。 第一封装基板设置在第一半导体管芯的第一表面上。 第一模塑料包围第一半导体管芯和第一封装衬底。 第一再分布层（RDL）结构设置在第一模塑料上，其中插入第一封装衬底并电耦合在第一半导体管芯和第一RDL结构之间。

公开(公告)号：US20160343685A1

公开(公告)日：2016-11-24

申请号：US15071559

申请日：2016-03-16

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ching-Wen HSIAO ,  I-Hsuan PENG

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/31 ,  H01L21/78 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/522 ,  H01L25/16

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/221 ,  H01L2224/32145 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2224/19

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die. The first RDL structure is positioned between the first semiconductor die and the second RDL structure.

Abstract translation: 提供半导体封装组件。 半导体封装组件包括第一半导体封装。 第一半导体封装包括第一半导体管芯。 第一再分配层（RDL）结构耦合到第一半导体管芯。 半导体封装组件还包括结合到第一半导体封装的第二半导体封装。 第二半导体封装包括第二半导体管芯。 第二半导体管芯的有源表面面向第一半导体管芯的有效表面。 第二RDL结构耦合到第二半导体管芯。 第一RDL结构位于第一半导体管芯和第二RDL结构之间。

公开(公告)号：US20160329299A1

公开(公告)日：2016-11-10

申请号：US15130994

申请日：2016-04-17

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Nai-Wei LIU ,  Ching-Wen HSIAO ,  Wei-Che HUANG

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/66 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025

Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die and a first molding compound that surrounds the first semiconductor die are disposed on the first surface of the first RDL structure. An IMD structure having a conductive layer with an antenna pattern or a conductive shielding layer is disposed on the first molding compound and the first semiconductor die.

Abstract translation: 提供了包括第一半导体封装的半导体封装结构。 第一半导体封装包括第一半导体封装，其包括具有第一表面和与其相反的第二表面的第一再分配层（RDL）结构。 围绕第一半导体管芯的第一半导体管芯和第一模塑料被设置在第一RDL结构的第一表面上。 具有天线图案或导电屏蔽层的导电层的IMD结构设置在第一模塑料和第一半导体芯片上。