Ball grid array package with thermally-enhanced heat spreader
    34.
    发明申请
    Ball grid array package with thermally-enhanced heat spreader 审中-公开
    具有热增强散热器的球栅阵列封装

    公开(公告)号:US20060278975A1

    公开(公告)日:2006-12-14

    申请号:US11148176

    申请日:2005-06-09

    IPC分类号: H01L23/10

    摘要: A ball grid array (BGA) package having a thermally enhanced dummy chip is provided. In one embodiment, the package comprises a substrate. A chip is attached to the substrate. A heat spreader is disposed over the chip, and a dummy chip is disposed between the heat spreader and the chip. In one embodiment, the dummy chip is pre-attached to the heat spreader prior to placement in the BGA package. With the coefficient of thermal expansion (CTE) of the dummy chip being approximately equal to the CTE of the chip, the stress in the BGA package is reduced, thereby reducing interface delamination among the components of the BGA package.

    摘要翻译: 提供具有热增强型伪芯片的球栅阵列(BGA)封装。 在一个实施例中,封装包括衬底。 芯片附着在基板上。 散热器设置在芯片上,虚设芯片设置在散热器和芯片之间。 在一个实施例中,虚拟芯片在放置在BGA封装之前预先附接到散热器。 由于虚拟芯片的热膨胀系数(CTE)大致等于芯片的CTE,所以BGA封装中的应力减小,从而减少BGA封装的部件之间的界面分层。

    Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA)
    37.
    发明授权
    Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA) 有权
    高性能倒装芯片BGA(HPFCBGA)的散热增强

    公开(公告)号:US07026711B2

    公开(公告)日:2006-04-11

    申请号:US10737496

    申请日:2003-12-16

    摘要: A microelectronic package comprising a device substrate having first and second opposing surfaces and comprising a plurality of microelectronic devices. The microelectronic package also includes a plurality of electrically conductive members coupled to corresponding ones of the plurality of microelectronics device and extending away from the first surface. A thermally conductive layer is located on the second surface of the device substrate, and a package substrate is coupled to the device substrate, the package substrate having a plurality of electrically conductive traces coupled to corresponding ones of the plurality of electrically conductive members.

    摘要翻译: 一种微电子封装,其包括具有第一和第二相对表面并且包括多个微电子器件的器件衬底。 微电子封装还包括耦合到多个微电子器件中的相应微电子器件并且远离第一表面延伸的多个导电构件。 导热层位于器件衬底的第二表面上,并且封装衬底耦合到器件衬底,封装衬底具有耦合到多个导电构件中的相应导电构件的多个导电迹线。

    Anti-bow zip lead frame design
    40.
    发明授权
    Anti-bow zip lead frame design 失效
    反弓拉链引线框设计

    公开(公告)号:US5150194A

    公开(公告)日:1992-09-22

    申请号:US691586

    申请日:1991-04-24

    IPC分类号: H01L23/495

    摘要: A new and improved integrated circuit lead frame to be used to reduce bowing during the assembly of conventional microcircuits is described, wherein a conventional die attach paddle is supported on one side by at least one tie bar, extending conventionally between the paddle and the lead finger support structure also known as dam bars, and supported on the opposing side by a plurality of tie bars which are attached on their opposing ends to a novel support beam. This support beam extends between opposing side of the lead frame and provides independent support for the tie bars on the one side and permits dimensional and angular symmetry, similarity and parity to be achieved in the location of all of the tie bars in order to optimize the stability and integrity of the die pad and reduce bowing after the encapsulation process.

    摘要翻译: 描述了一种新的改进的集成电路引线框架,用于在常规微电路的组装期间减少弯曲,其中传统的芯片附接板在一侧由至少一个连接杆支撑,其通常在桨和引线指 支撑结构也称为挡板,并且通过多个连接杆在相对侧上支撑,所述连接杆在其相对端附接到新的支撑梁。 该支撑梁在引线框架的相对侧之间延伸,并且在一侧上为连杆提供独立的支撑,并且允许在所有连接杆的位置中实现尺寸和角度对称性,相似性和奇偶校验,以便优化 芯片焊盘的稳定性和完整性,并且在封装工艺之后减少弯曲。