公开(公告)号：US20190131977A1

公开(公告)日：2019-05-02

申请号：US15886179

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: H03K19/21 ,  H03K19/18 ,  G06N3/063

Abstract: A hardware cell and method for performing a digital XNOR of an input signal and weights are described. The hardware cell includes input lines, a plurality of pairs of magnetic junctions, output transistors and at least one selection transistor coupled with the output transistors. The input lines receive the input signal and its complement. The magnetic junctions store the weight. Each magnetic junction includes a reference layer, a free layer and a nonmagnetic spacer layer between the reference layer and the free layer. The free layer has stable magnetic states and is programmable using spin-transfer torque and/or spin-orbit interaction torque. The first magnetic junction of a pair receives the input signal. The second magnetic junction of the pair receives the input signal complement. The output transistors are coupled with the magnetic junctions such that each pair of magnetic junctions forms a voltage divider. The output transistors form a sense amplifier.

公开(公告)号：US20190131182A1

公开(公告)日：2019-05-02

申请号：US15877931

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/225 ,  H01L21/268 ,  H01L21/324 ,  H01L21/02

Abstract: A method for providing a semiconductor device and the device so formed are described. A doped semiconductor layer is deposited on a semiconductor underlayer. At least a portion of the semiconductor underlayer is exposed. A dopant for the doped semiconductor layer is selected from a p-type dopant and an n-type dopant. An ultraviolet-assisted low temperature (UVLT) anneal of the doped semiconductor layer is performed in an ambient. The ambient is selected from an oxidizing ambient and a nitriding ambient. The oxidizing ambient is used for the n-type dopant. The nitriding ambient is used for the p-type dopant. A sacrificial layer is formed by the doped semiconductor layer during the UVLT anneal. The dopant is driven into the portion of the semiconductor underlayer from the doped semiconductor layer by the UVLT anneal, thereby forming a doped semiconductor underlayer. The sacrificial layer is then removed.

公开(公告)号：US20190122891A1

公开(公告)日：2019-04-25

申请号：US15898420

申请日：2018-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/28158 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

公开(公告)号：US20180286764A1

公开(公告)日：2018-10-04

申请号：US15997596

申请日：2018-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L21/8238 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/04 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: A field effect transistor includes a fin having a stack of nanowire-like channel regions including at least first and a second nanowire-like channel regions, source and drain electrodes on opposite sides of the fin, a dielectric separation region including a dielectric material between the first and second nanowire-like channel regions, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The dielectric separation region extending completely from a surface of the second nanowire-like channel region facing the first nanowire-like channel region to a surface of the first nanowire-like channel region facing the second nanowire-like channel region. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer of the gate stack does not extend between the first and second nanowire-like channel regions.

公开(公告)号：US20180174034A1

公开(公告)日：2018-06-21

申请号：US15488419

申请日：2017-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/808 ,  H01L29/66

CPC classification number: G06N3/0635 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/8083

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US09831323B2

公开(公告)日：2017-11-28

申请号：US15267134

申请日：2016-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Robert Christopher Bowen ,  Borna J. Obradovic ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/201 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/04 ,  H01L21/465

CPC classification number: H01L29/6681 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02485 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/465 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/7853

Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter.

公开(公告)号：US20170098661A1

公开(公告)日：2017-04-06

申请号：US15210867

申请日：2016-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Rwik Sengupta ,  Wei-E Wang ,  Ryan Hatcher ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L23/528 ,  H01L29/24 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/84 ,  H01L23/522 ,  H01L29/45

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/78681

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.

公开(公告)号：US09583590B2

公开(公告)日：2017-02-28

申请号：US14698402

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66522 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include InyGa1−yAs, and y is in a range of about 0.3 to about 0.5.

Abstract translation: 提供了形成finFET的方法。 所述方法可以包括在衬底上形成包括铟（In）的鳍状沟道区域，形成与衬底上的沟道区相邻的深源极/漏极区域，并在沟道区域和深度之间形成源极/漏极延伸区域 源/漏区。 源极/漏极延伸区域的相对侧壁可以分别接触沟道区域和深源极/漏极区域，并且源极/漏极延伸区域可以包括In y Ga 1-y As，y在约0.3至约0.5的范围内。

公开(公告)号：US20160111284A1

公开(公告)日：2016-04-21

申请号：US14918954

申请日：2015-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L21/283 ,  H01L21/306

CPC classification number: H01L29/0669 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L29/0665 ,  H01L29/1054 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7783

Abstract: Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer An is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A; proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that to hold the nanosheets in place after selective etch of the sacrificial layers; and selectively removing sacrificial layers A to all non-sacrificial layers B and C, while the remaining layers in the stack are held in place by the pillar structures so that after removal of the sacrificial layers An, each of the sub-stacks contains the non-sacrificial layers B and C.

Abstract translation: 示例性实施例提供制造具有一个或多个子堆叠的纳米片堆叠结构。 示例性实施例的方面包括：生长一个或多个子堆叠的外延晶体初始堆叠，每个子堆叠具有至少三个层，牺牲层A和至少两个不同的非牺牲层B和C 具有不同的材料性质，其中非牺牲层B和C层保持低于在所有加工期间对应于亚稳态的热力学或动力学临界厚度，并且其中牺牲层An仅被放置在每个的顶部或底部 并且每个子堆叠使用牺牲层A之一连接到顶部或底部的相邻子堆叠; 继续纳米片装置的制造流程，使得在外延晶体堆叠的每个端部处形成柱结构，以在选择性蚀刻牺牲层之后将纳米片保持在适当位置; 并且将牺牲层A选择性地去除所有非牺牲层B和C，而堆叠中的其余层被柱结构保持就位，使得在去除牺牲层An之后，每个子堆包含非牺牲层 - 层B和C.

公开(公告)号：US09112130B2

公开(公告)日：2015-08-18

申请号：US14478344

申请日：2014-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Robert C. Bowen

IPC: H03K19/195 ,  H01L49/00 ,  H01L29/16 ,  H01L29/20 ,  H01L29/88 ,  H01L29/06

CPC classification number: H01L49/006 ,  H01L29/0669 ,  H01L29/1606 ,  H01L29/20 ,  H01L29/88

Abstract: A logic device is provided which includes an electron monochromator. The electron monochromator includes a quantum dot disposed between first and second tunneling barriers, an emitter coupled to the first tunneling barrier, and a collector coupled to the second tunneling barrier. The logic device also includes a quantum interference device. The quantum interference device includes a source which is coupled to the collector of the electron monochromator.

Abstract translation: 提供了一种包括电子单色仪的逻辑器件。 电子单色仪包括设置在第一和第二隧道势垒之间的量子点，耦合到第一隧道势垒的发射极和耦合到第二隧穿势垒的集电极。 逻辑器件还包括量子干涉器件。 量子干涉装置包括耦合到电子单色仪的集电极的源。