公开(公告)号：US10347355B2

公开(公告)日：2019-07-09

申请号：US15795595

申请日：2017-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC: G11C29/44 ,  G11C29/56 ,  G11B20/18 ,  G01R31/3187 ,  G06F11/27 ,  G06F11/20 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/00 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/36 ,  G11C29/42

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

公开(公告)号：US10319858B2

公开(公告)日：2019-06-11

申请号：US16128152

申请日：2018-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Kim ,  Kyung-Seok Oh ,  Cheol Kim ,  Heon-Jong Shin ,  Jong-Ryeol Yoo ,  Hyun-Jung Lee ,  Seong-Hoon Jeong

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.

公开(公告)号：US20190130958A1

公开(公告)日：2019-05-02

申请号：US16005880

申请日：2018-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol Kim ,  Kee-Won Kwon ,  Ji-Su Min ,  Rak-Joo Sung ,  Sung-gi Ahn

IPC: G11C11/22 ,  G11C5/06 ,  G11C7/12

CPC classification number: G11C11/2293 ,  G11C5/063 ,  G11C7/12 ,  G11C15/04 ,  G11C15/043

Abstract: A memory device includes a storage circuit, a first driving circuit, and a second driving circuit. The storage circuit stores first data and compares the first data and second data. The first driving circuit selectively drives a matching line to a first logic state, depending on a comparison result of the first data and the second data by the storage circuit. The second driving circuit drives the matching line to a second logic state regardless of the comparison result.

公开(公告)号：US20170117033A1

公开(公告)日：2017-04-27

申请号：US15224683

申请日：2016-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-yeon Doo ,  Tae-young Oh ,  Cheol Kim ,  Geun-tae Park

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/40626 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4091

Abstract: Provided is a method of refreshing a memory device by controlling a self-refresh cycle according to temperature. In the method, first self-refresh and second self-refresh are performed according to inner temperature of the memory device and a self-refresh cycle is controlled such that an all-bank-refresh (ABR) operation is not performed simultaneously with the start of the second self-refresh. The ABR operation is performed at the start of third self-refresh when the sum of a section of the first self-refresh in which the ABR operation is not performed and a section of the second self-refresh in which the ABR operation is not performed corresponds to a self-refresh cycle.

公开(公告)号：US09570132B2

公开(公告)日：2017-02-14

申请号：US14803119

申请日：2015-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Kim ,  Young-soo Sohn ,  Sang-Ho Shin

IPC: G11C8/00 ,  G11C8/06 ,  H01L25/065 ,  G11C29/00

CPC classification number: G11C8/06 ,  G11C29/76 ,  G11C29/785 ,  H01L25/0657 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively. Each semiconductor die includes a die input-output pad unit, a memory region and a conversion block. The die input-output pad unit includes a plurality of input-output terminals respectively connected to the input-output pins of the chip input-output pad unit. The memory region includes an activated region corresponding to a portion of the full memory capacity and a deactivated region corresponding to a remainder portion of the full memory capacity. The conversion block connects the activated region except the deactivated region to the die input-output pad unit.

Abstract translation: 存储器芯片包括芯片输入 - 输出焊盘单元，多个半导体管芯。 芯片输入输出焊盘单元包括连接到外部设备的多个输入输出引脚，并且多个半导体管芯分别连接到芯片输入 - 输出焊盘单元并具有完全存储器容量。 每个半导体管芯包括管芯输入 - 输出焊盘单元，存储区域和转换块。 管芯输入 - 输出焊盘单元包括分别连接到芯片输入 - 输出焊盘单元的输入 - 输出引脚的多个输入 - 输出端子。 存储器区域包括对应于全部存储器容量的一部分的激活区域和对应于完整存储器容量的剩余部分的去激活区域。 转换块将去激活区域之外的激活区域连接到管芯输入 - 输出焊盘单元。

公开(公告)号：US08976564B2

公开(公告)日：2015-03-10

申请号：US13748773

申请日：2013-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Il Lim ,  Cheol Kim ,  Sang-Ho Shin

IPC: G11C17/00 ,  G11C17/16 ,  G11C29/00

CPC classification number: G11C17/00 ,  G11C17/16 ,  G11C29/785

Abstract: A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.

Abstract translation: 存储器件包括包括多个反熔丝单元的反熔丝单元阵列。 每个反熔丝单元包括连接到公共节点的第一单元晶体管，连接到公共节点的第二单元晶体管和连接到公共节点的存取晶体管。 第一单元晶体管被配置为存储数据，并且第二单元晶体管被配置为当第一单元晶体管具有缺陷数据时存储数据。

公开(公告)号：US08906757B2

公开(公告)日：2014-12-09

申请号：US13674386

申请日：2012-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Cheol Kim ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract translation: 提供了形成半导体器件的图案的方法。 所述方法可以包括在半导体衬底上形成硬掩模膜。 所述方法可以包括形成在硬掩模膜上彼此间隔开的第一和第二牺牲膜图案。 所述方法可以包括在第一牺牲膜图案的相对侧壁上形成第一间隔物，以及在第二牺牲膜图案的相对侧壁上形成第二间隔物。 所述方法可以包括去除第一和第二牺牲膜图案。 所述方法可以包括修整第二间隔物，使得第二间隔物的线宽变得小于第一间隔物的线宽。 所述方法可以包括通过使用第一间隔物和修剪的第二间隔物作为蚀刻掩模蚀刻硬掩模膜来形成第一和第二硬掩模膜图案。

公开(公告)号：US20140035048A1

公开(公告)日：2014-02-06

申请号：US13949289

申请日：2013-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Sun Lee ,  Myeongcheol Kim ,  Cheol Kim ,  Sanghyun Lee

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/78 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include a transistor on a substrate comprising a gate insulating pattern, a gate electrode and an impurity region, a shared contact plug electrically connected to the gate electrode and the impurity region, and an etch-stop layer between side surfaces of the gate electrode and the shared contact. The shared contact plug may include a first conductive pattern electrically connected to the first impurity region and a second conductive pattern electrically connected to the gate electrode, and a top surface of the first conductive pattern may be higher than a top surface of the gate electrode.

Abstract translation: 提供半导体器件及其制造方法。 器件可以包括在包括栅极绝缘图案，栅极电极和杂质区域的衬底上的晶体管，电连接到栅极电极和杂质区域的共用接触插塞以及栅极侧表面之间的蚀刻停止层 电极和共用触点。 共享接触插头可以包括电连接到第一杂质区域的第一导电图案和电连接到栅电极的第二导电图案，并且第一导电图案的顶表面可以高于栅电极的顶表面。

公开(公告)号：US12046599B2

公开(公告)日：2024-07-23

申请号：US17522051

申请日：2021-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol Kim ,  Jongchul Park ,  Hyunho Jung

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate having first and second active regions. A first active pattern is on the first active region and includes first source/drain patterns and a first channel pattern therebetween. A second active pattern is on the second active region and includes second source/drain patterns and a second channel pattern therebetween. A gate electrode includes a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern. A gate cutting pattern is between the first and second gate electrodes and separates the first and second gate electrodes from each other. A pair of gate spacers is on opposite sidewalls of the first gate electrode extending along opposite sidewalls of the gate cutting pattern towards the second gate electrode. The gate cutting pattern includes first to third parts having maximum widths that increase from the first to the third part.

公开(公告)号：US20240222299A1

公开(公告)日：2024-07-04

申请号：US18402021

申请日：2024-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwan Young CHOI ,  Seok Hyun Lee ,  Cheol Kim ,  Seok Geun Ahn

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L24/08 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/05017 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/08145 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor package comprises a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first substrate, a first semiconductor device layer disposed on the first substrate, a first chip wiring layer disposed on the first semiconductor device layer, and a first bonding pad directly connected to the first chip wiring layer and that includes a first dishing formed thereon. The second semiconductor chip includes a second substrate, a first through-via that penetrates through the second substrate, and a second bonding pad directly connected to the first through-via and that includes a second dishing formed thereon. The first semiconductor chip and the second semiconductor chip are bonded to each other and the first bonding pad and the second bonding pad face each other, and a gold bonding layer fills the first dishing of the first bonding pad and the second dishing of the second bonding pad.