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31.发明授权Method for fabricating last level copper-to-C4 connection with interfacial cap structure 有权用于制造具有界面盖结构的最后一级铜对C4连接的方法公开(公告)号：US07863183B2
公开(公告)日：2011-01-04
申请号：US11306983
申请日：2006-01-18
IPC分类号： H01L21/4763
CPC分类号： H01L21/288 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05147 , H01L2224/05575 , H01L2224/05599 , H01L2224/1148 , H01L2224/13007 , H01L2224/13022 , H01L2224/13111 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/01015
摘要： The present invention relates to a method for fabricating a semiconductor device with a last level copper-to-C4 connection that is essentially free of aluminum. Specifically, the last level copper-to-C4 connection comprises an interfacial cap structure containing CoWP, NiMoP, NiMoB, NiReP, NiWP, and combinations thereof. Preferably, the interfacial cap structure comprises at least one CoWP layer. Such a CoWP layer can be readily formed over a last level copper interconnect by a selective electroless plating process.
摘要翻译： 本发明涉及一种用于制造具有基本上不含铝的最后一级铜对C4连接的半导体器件的方法。 具体地说，最后一级的铜对C4连接包括含有CoWP，NiMoP，NiMoB，NiReP，NiWP及其组合的界面盖结构。 优选地，界面帽结构包括至少一个CoWP层。 这种CoWP层可以通过选择性无电镀方法容易地在最后一级铜互连上形成。
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公开(公告)号：US07825511B2
公开(公告)日：2010-11-02
申请号：US12357484
申请日：2009-01-22
IPC分类号： H01L23/12
CPC分类号： H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/03462 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05006 , H01L2224/0501 , H01L2224/05083 , H01L2224/05546 , H01L2224/05624 , H01L2224/114 , H01L2224/11462 , H01L2224/1147 , H01L2224/11472 , H01L2224/11474 , H01L2224/116 , H01L2224/11849 , H01L2224/11902 , H01L2224/13006 , H01L2224/13023 , H01L2224/1308 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/16 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/00014 , H01L2224/13099
摘要： A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP with a bottom conductive layer of the barrier metal stack removed by etching. The diffusion barrier and C4 solder bump may be formed by electroless plating, in one embodiment, using a maskless technique, or by an electroplating techniques using a patterned mask. This allows the pitch of the C4 solder bumps to be reduced.
摘要翻译： 一种用于在形成用于BLM（限流冶金）的C4焊料凸块并提高C4间距时消除底切的系统和方法。 在该过程中，在金属焊盘层上方沉积阻挡层金属堆叠。 通过CMP对阻挡层金属（例如Cu）的顶层进行图案化，通过蚀刻去除阻挡金属叠层的底部导电层。 扩散阻挡层和C4焊料凸点可以通过化学镀来形成，在一个实施例中，使用无掩模技术，或通过使用图案化掩模的电镀技术形成。 这样可以减少C4焊料凸点的间距。
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33.发明申请Structures and Methods for Improving Solder Bump Connections in Semiconductor Devices 有权用于改善半导体器件中焊料凸点连接的结构和方法公开(公告)号：US20100164096A1
公开(公告)日：2010-07-01
申请号：US12344711
申请日：2008-12-29
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H01L23/488 , H01L21/44
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05011 , H01L2224/05017 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05551 , H01L2224/05555 , H01L2224/05557 , H01L2224/05644 , H01L2224/13006 , H01L2224/13022 , H01L2224/13025 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2924/00013 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01093 , H01L2924/0132 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/0103 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a via formed in a dielectric layer to expose a contact pad and a capture pad formed in the via and over the dielectric layer. The capture pad has openings over the dielectric layer to form segmented features. The solder bump is deposited on the capture pad and the openings over the dielectric layer.
摘要翻译： 具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。 该结构包括在电介质层中形成的通孔，以露出形成在通孔中和电介质层上的接触焊盘和捕获焊盘。 捕获垫在电介质层上具有开口以形成分段特征。 焊料凸块沉积在捕获垫上并且在介电层上沉积开口。
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公开(公告)号：US07601628B2
公开(公告)日：2009-10-13
申请号：US11561437
申请日：2006-11-20
IPC分类号： H01L21/60
CPC分类号： H01L23/3171 , B23K1/0016 , B23K1/20 , B23K20/004 , B23K2101/40 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/85 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2224/16145 , H01L2224/45124 , H01L2224/45139 , H01L2224/45147 , H01L2224/48463 , H01L2224/48724 , H01L2224/48747 , H01L2224/48847 , H01L2224/85011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/00014 , H01L2224/48824 , H01L2924/00
摘要： Methods of forming wire and solder bonds are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide layer; forming in a material a first opening to the silicon oxide layer over the wire bond metal region and a second opening exposing the solder bond metal region; forming the solder bond to the solder bond metal region while the wire bond metal region is covered; exposing the wire bond metal region including removing the silicon oxide layer to the wire bond metal region; and forming the wire bond to the wire bond metal region. Wire bonds and solder bonds can be made accessible on a single multi-part wafer (MPW) or on a single chip, if necessary, and can be formed substantially simultaneously.
摘要翻译： 公开了形成线和焊料接合的方法。 在一个实施例中，一种方法包括提供一种结构，其包括用于引线键合的引线接合金属区域和用于焊接接合的焊接接合金属区域，两个区域均由氧化硅层上的氮化硅层覆盖; 在材料上形成在所述引线接合金属区域上的所述氧化硅层的第一开口和暴露所述焊料接合金属区域的第二开口; 在焊接金属区域被覆盖的同时，将焊料接合到焊料接合金属区域; 将引线键合金属区域暴露，包括将氧化硅层去除到引线键合金属区域; 并且将线接合形成到引线接合金属区域。 如果需要，线接合和焊接接合可以在单个多部分晶片（MPW）或单个芯片上访问，并且可以基本上同时形成。
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公开(公告)号：US20090218688A1
公开(公告)日：2009-09-03
申请号：US12039134
申请日：2008-02-28
申请人： Stephen P. Ayotte , Timothy H. Daubenspeck , Jeffrey Gambino , Christopher D. Muzzy , David L. Questad , Wolfgang Sauter
发明人： Stephen P. Ayotte , Timothy H. Daubenspeck , Jeffrey Gambino , Christopher D. Muzzy , David L. Questad , Wolfgang Sauter
IPC分类号： H01L23/52
CPC分类号： H01L24/11 , H01L2224/05567 , H01L2224/05573 , H01L2224/13099 , H01L2224/16 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/05599
摘要： A semiconductor structure includes at least one bond pad. An insulator layer is on the surface of the semiconductor chip and on a portion of the bond pad. The polyimide layer comprises a bottom surface contacting and coplanar with the surface of the semiconductor chip, a top surface opposite and parallel to the bottom surface of the polyimide layer, and a sloped side between corresponding ends of the top surface of the polyimide layer and the bottom surface of the polyimide layer. The sloped side joins the bottom surface of the polyimide layer at the top surface of the bond pad. The sloped side of the polyimide layer forms an angle less than 50° with the bottom surface of the polyimide layer.
摘要翻译： 半导体结构包括至少一个接合焊盘。 绝缘体层位于半导体芯片的表面上和接合焊盘的一部分上。 聚酰亚胺层包括与半导体芯片的表面接触和共面的底表面，与聚酰亚胺层的底表面相反并平行的顶表面，以及在聚酰亚胺层的顶表面的相应端之间的倾斜侧和 聚酰亚胺层的底面。 倾斜侧在接合焊盘的顶表面处连接聚酰亚胺层的底表面。 聚酰亚胺层的倾斜侧与聚酰亚胺层的底面形成小于50°的角度。
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公开(公告)号：US07521287B2
公开(公告)日：2009-04-21
申请号：US11561434
申请日：2006-11-20
IPC分类号： H01L21/60
CPC分类号： B23K1/20 , B23K1/0016 , B23K20/004 , B23K20/24 , B23K2101/40 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/80 , H01L24/85 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05548 , H01L2224/1147 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2224/13124 , H01L2224/13147 , H01L2224/16 , H01L2224/45124 , H01L2224/45147 , H01L2224/45155 , H01L2224/48091 , H01L2224/48463 , H01L2224/48699 , H01L2224/48799 , H01L2224/85011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/00 , H01L2224/05599
摘要： Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region. Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.
摘要翻译： 公开了形成线和焊接结合结构的方法。 在一个实施例中，一种方法包括提供包括用于引线键合的引线接合金属区域和用于焊接接合的焊接接合金属区域的结构; 仅在引线键合金属区域上形成保护层; 在引线接合金属区域和焊料接合金属区域上的氧化硅层上形成氮化硅层; 在焊接金属区域被覆盖的同时，形成与焊接金属区域的焊料接合; 使引线接合金属区域露出，包括去除保护层; 并且将线接合形成到引线接合金属区域。 如果需要，可以在单个多部件晶片（MPW）晶片上或单个芯片上使引线键合和焊接结合结构可访问。
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37.发明授权Method of forming a crack stop void in a low-k dielectric layer between adjacent fuses 失效在相邻保险丝之间的低k电介质层中形成裂纹停止空隙的方法公开(公告)号：US07479447B2
公开(公告)日：2009-01-20
申请号：US11277398
申请日：2006-03-24
申请人： Timothy H. Daubenspeck , Christopher D. Muzzy , Paul S. McLaughlin , Judith A. Wright , Jean E. Wynne , Dae Young Jung
发明人： Timothy H. Daubenspeck , Christopher D. Muzzy , Paul S. McLaughlin , Judith A. Wright , Jean E. Wynne , Dae Young Jung
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A crack stop void is formed in a low-k dielectric layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The crack stop void is formed simultaneously with the formation of an interconnect structure.
摘要翻译： 在相邻熔丝结构之间的低k电介质层中形成裂纹阻挡空隙，用于在保险丝熔断操作期间防止相邻熔丝结构之间的裂纹传播。 裂缝停止空隙与形成互连结构同时形成。
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公开(公告)号：US20080244904A1
公开(公告)日：2008-10-09
申请号：US12138531
申请日：2008-06-13
IPC分类号： H01B19/00
CPC分类号： H01L23/544 , H01L22/24 , H01L22/32 , H01L22/34 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/48 , H01L2223/5448 , H01L2224/02166 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05181 , H01L2224/05624 , H01L2224/05666 , H01L2224/05681 , H01L2224/13099 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01022 , H01L2924/01033 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204 , Y10T29/49227 , H01L2224/45099
摘要： An integrated circuit has a wiring layer below an insulator layer. A pad comprises a conductive material that is on the insulator layer. The pad has a wirebond connection region and a probe pad region. An inspection mark is between the wirebond connection region and the probe pad region. The inspection mark comprises an opening in the insulator layer that is filled with the conductive material. In addition, a contact that is through the insulator layer is adapted to electrically connect the conductor wire in the wiring layer to the pad. The contact is formed of the same conductive material used for the pad and the inspection mark.
摘要翻译： 集成电路在绝缘体层下方具有布线层。 衬垫包括位于绝缘体层上的导电材料。 焊盘具有引线连接区域和探针焊盘区域。 导线连接区域和探针焊盘区域之间的检查标记。 检查标记包括填充有导电材料的绝缘体层中的开口。 此外，穿过绝缘体层的接触件适于将布线层中的导线电连接到焊盘。 接触由用于垫和检查标记的相同的导电材料形成。
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公开(公告)号：US20080119036A1
公开(公告)日：2008-05-22
申请号：US11561437
申请日：2006-11-20
IPC分类号： H01L21/44
CPC分类号： H01L23/3171 , B23K1/0016 , B23K1/20 , B23K20/004 , B23K2101/40 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/85 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2224/16145 , H01L2224/45124 , H01L2224/45139 , H01L2224/45147 , H01L2224/48463 , H01L2224/48724 , H01L2224/48747 , H01L2224/48847 , H01L2224/85011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/00014 , H01L2224/48824 , H01L2924/00
摘要： Methods of forming wire and solder bonds are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide layer; forming in a material a first opening to the silicon oxide layer over the wire bond metal region and a second opening exposing the solder bond metal region; forming the solder bond to the solder bond metal region while the wire bond metal region is covered; exposing the wire bond metal region including removing the silicon oxide layer to the wire bond metal region; and forming the wire bond to the wire bond metal region. Wire bonds and solder bonds can be made accessible on a single multi-part wafer (MPW) or on a single chip, if necessary, and can be formed substantially simultaneously.
摘要翻译： 公开了形成线和焊料接合的方法。 在一个实施例中，一种方法包括提供一种结构，其包括用于引线键合的引线接合金属区域和用于焊接接合的焊接接合金属区域，两个区域均由氧化硅层上的氮化硅层覆盖; 在材料上形成在所述引线接合金属区域上的所述氧化硅层的第一开口和暴露所述焊料接合金属区域的第二开口; 在焊接金属区域被覆盖的同时，将焊料接合到焊料接合金属区域; 将引线键合金属区域暴露，包括将氧化硅层去除到引线键合金属区域; 并且将线接合形成到引线接合金属区域。 如果需要，线接合和焊接接合可以在单个多部分晶片（MPW）或单个芯片上访问，并且可以基本上同时形成。
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公开(公告)号：US20080119035A1
公开(公告)日：2008-05-22
申请号：US11561434
申请日：2006-11-20
IPC分类号： H01L21/44
CPC分类号： B23K1/20 , B23K1/0016 , B23K20/004 , B23K20/24 , B23K2101/40 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/80 , H01L24/85 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05548 , H01L2224/1147 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2224/13124 , H01L2224/13147 , H01L2224/16 , H01L2224/45124 , H01L2224/45147 , H01L2224/45155 , H01L2224/48091 , H01L2224/48463 , H01L2224/48699 , H01L2224/48799 , H01L2224/85011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/00 , H01L2224/05599
摘要： Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region. Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.
摘要翻译： 公开了形成线和焊接结合结构的方法。 在一个实施例中，一种方法包括提供包括用于引线键合的引线接合金属区域和用于焊接接合的焊接接合金属区域的结构; 仅在引线键合金属区域上形成保护层; 在引线接合金属区域和焊料接合金属区域上的氧化硅层上形成氮化硅层; 在焊接金属区域被覆盖的同时，形成与焊接金属区域的焊料接合; 使引线接合金属区域露出，包括去除保护层; 并且将线接合形成到引线接合金属区域。 如果需要，可以在单个多部件晶片（MPW）晶片上或单个芯片上使引线键合和焊接结合结构可访问。
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