公开(公告)号：US20180323058A1

公开(公告)日：2018-11-08

申请号：US15590004

申请日：2017-05-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC分类号： H01L21/02 ,  C09G1/02 ,  C08K5/42 ,  C08K5/14

CPC分类号： H01L21/02074 ,  H01L21/02065 ,  H01L21/32115 ,  H01L29/00

摘要： A method for post chemical mechanical polishing clean is provided in the present invention, which include the steps of providing a substrate, performing a chemical mechanical polishing process, and performing a plurality of cleaning processes sequentially substrate using solutions of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) with different ratios and at different temperatures.

公开(公告)号：US09960084B1

公开(公告)日：2018-05-01

申请号：US15339949

申请日：2016-11-01

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Wen-Jiun Shen ,  Yu-Ren Wang

IPC分类号： H01L21/8238 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L21/311 ,  H01L27/092

CPC分类号： H01L21/823821 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/6653 ,  H01L29/7848 ,  H01L29/785

摘要： The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.

公开(公告)号：US09882022B2

公开(公告)日：2018-01-30

申请号：US15592150

申请日：2017-05-10

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Ming Kuo ,  Po-Jen Chuang ,  Fu-Jung Chuang ,  Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Fu-Yu Tsai

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/49 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

摘要： A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, a gate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.

公开(公告)号：US09847247B2

公开(公告)日：2017-12-19

申请号：US15590114

申请日：2017-05-09

申请人： UNITED MICROELECTRONICS CORP.

发明人： Ping-Wei Huang ,  Keng-Jen Lin ,  Yi-Hui Lin ,  Yu-Ren Wang

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/785

摘要： A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.

公开(公告)号：US20170309485A1

公开(公告)日：2017-10-26

申请号：US15137010

申请日：2016-04-25

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Hsu Ting ,  Neng-Hui Yang

IPC分类号： H01L21/268 ,  H01L21/687 ,  H01L21/67 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/265 ,  H01L29/66

CPC分类号： H01L21/2686 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67115 ,  H01L21/68785 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834

摘要： An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.

公开(公告)号：US20170263730A1

公开(公告)日：2017-09-14

申请号：US15064275

申请日：2016-03-08

申请人： United Microelectronics Corp.

发明人： Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC分类号： H01L29/66 ,  H01L21/266 ,  H01L29/49 ,  H01L21/02

CPC分类号： H01L29/66492 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66636

摘要： A semiconductor process including the following steps is provided. An epitaxial layer is formed on a substrate. An oxide layer is formed on the epitaxial layer, wherein the oxide layer includes a chemical oxide layer, a high-temperature oxide (HTO) layer or a surface modification oxide layer. An ion implant process is performed to the epitaxial layer to form a doped region in the epitaxial layer. The oxide layer is removed by using a diluted hydrofluoric acid (DHF) solution after performing the ion implant process, wherein a volume ratio of water to a hydrofluoric acid (HF) in the DHF solution is 200:1 to 1000:1.

公开(公告)号：US20170162389A1

公开(公告)日：2017-06-08

申请号：US15439890

申请日：2017-02-22

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC分类号： H01L21/033 ,  H01L29/66 ,  H01L29/78 ,  H01L29/24 ,  H01L29/267 ,  H01L29/08 ,  H01L21/02 ,  H01L21/8238

CPC分类号： H01L21/0335 ,  H01L21/02521 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/3105 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A method for fabricating the semiconductor device is disclosed. A semiconductor substrate having a main surface is provided. A gate is formed on the main surface of the semiconductor substrate. An offset liner is formed on the sidewall of the gate. An ion implantation process is performed to form lightly doped drain (LDD) region in the semiconductor substrate. A spacer is formed on a sidewall of the gate. A cavity is recessed into the main surface of the semiconductor substrate. The cavity is adjacent to the spacer. An epitaxial layer is grown in the cavity. The spacer is then subjected to a surface treatment to form a dense oxide film on the spacer. A mask layer is deposited on the dense oxide film. The dense oxide film has a thickness that is smaller or equal to 12 angstroms.

公开(公告)号：US09634083B2

公开(公告)日：2017-04-25

申请号：US13710382

申请日：2012-12-10

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Liang Lin ,  Yu-Ren Wang ,  Ying-Wei Yen

IPC分类号： H01L21/20 ,  H01L29/06 ,  H01L21/441 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/02164 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/441 ,  H01L29/0603 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

摘要： A semiconductor structure includes a dielectric layer located on a substrate, wherein the dielectric layer includes nitrogen atoms, and the concentration of the nitrogen atoms in the dielectric layer is lower than 5% at a location wherein the distance between this location in the dielectric layer to the substrate is less than 20% of the thickness of the dielectric layer. Moreover, the present invention provides a semiconductor process including the following steps: a dielectric layer is formed on a substrate. Two annealing processes are performed in-situly on the dielectric layer, wherein the two annealing processes have different imported gases and different annealing temperatures.

公开(公告)号：US09570578B2

公开(公告)日：2017-02-14

申请号：US14619085

申请日：2015-02-11

申请人： UNITED MICROELECTRONICS CORP.

发明人： Keng-Jen Lin ,  Chien-Liang Lin ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC分类号： H01L29/66 ,  H01L21/285 ,  H01L21/28 ,  H01L29/49 ,  H01L21/322 ,  H01L29/51

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/28506 ,  H01L21/3221 ,  H01L29/4966 ,  H01L29/517

摘要： A gate forming process includes the following steps. A gate dielectric layer is formed on a substrate. A barrier layer is formed on the gate dielectric layer. A silicon seed layer and a silicon layer are sequentially and directly formed on the barrier layer, wherein the silicon seed layer and the silicon layer are formed by different precursors.

摘要翻译： 门形成工艺包括以下步骤。 在基板上形成栅极电介质层。 在栅介质层上形成阻挡层。 硅晶种层和硅层依次直接形成在阻挡层上，其中硅晶种层和硅层由不同的前体形成。

公开(公告)号：US09543408B1

公开(公告)日：2017-01-10

申请号：US14835730

申请日：2015-08-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yi-Hui Lin ,  Keng-Jen Lin ,  Chun-Yao Yang ,  Yu-Ren Wang

IPC分类号： H01L21/3205 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/3213 ,  H01L21/3215

CPC分类号： H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/32055 ,  H01L21/32139 ,  H01L21/32155 ,  H01L21/324 ,  H01L23/544 ,  H01L29/66795 ,  H01L2223/54426 ,  H01L2223/54453

摘要： A method of forming a patterned hark mask layer includes the following steps. A semiconductor substrate is provided. An amorphous silicon layer is formed on the semiconductor substrate. An implantation process is performed on the amorphous silicon layer. An annealing treatment is performed on the amorphous silicon layer after the implantation process. A patterned hard mask layer is formed on the amorphous silicon layer after the annealing treatment.

摘要翻译： 形成图案化掩模掩模层的方法包括以下步骤。 提供半导体衬底。 在半导体衬底上形成非晶硅层。 对非晶硅层进行注入工艺。 在植入处理之后对非晶硅层进行退火处理。 在退火处理之后，在非晶硅层上形成图案化的硬掩模层。