公开(公告)号：US20150234754A1

公开(公告)日：2015-08-20

申请号：US14702995

申请日：2015-05-04

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Donald C. Stark ,  Frederick A. Ware ,  Ely K. Tsern ,  Craig E. Hampel

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/10

CPC classification number: G06F13/1678 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0646 ,  G06F13/1657 ,  G06F13/4022 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1087 ,  G11C8/06 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/105 ,  G11C2207/108 ,  H05K1/117 ,  H05K1/14 ,  H05K2201/09954 ,  H05K2201/10189 ,  Y02D10/14

Abstract: Described are memory systems in which a memory controller issues commands and addresses to multiple memory modules that collectively support each read and write transactions. A common set of control signal lines from the controller communicates the same command and address signals to the modules. For write commands, the controller sends subsets of write data to each module over a respective subset of data lines. For read commands, each module responds with a subset of the requested data over the respective subset of data lines. The memory modules can be width configurable so that a single full-width module can connect to both subsets of data lines to convey full-width data, or two half-width modules can connect one each to the subsets of data lines.

Abstract translation: 描述的是其中存储器控制器向共同支持每个读取和写入事务的多个存储器模块发出命令和地址的存储器系统。 来自控制器的一组共同的控制信号线将相同的命令和地址信号传送给模块。 对于写命令，控制器通过数据线的相应子集向每个模块发送写数据子集。 对于读取命令，每个模块通过数据线的相应子集来响应所请求数据的子集。 存储器模块可以宽度可配置，使得单个全宽度模块可以连接到数据线的两个子集以传送全宽数据，或者两个半宽度模块可以将每个数据线连接到数据线的子集。

公开(公告)号：US09112739B2

公开(公告)日：2015-08-18

申请号：US14225580

申请日：2014-03-26

Applicant: Rambus Inc.

Inventor： Ramin Farjad-Rad

IPC: H04L25/03

CPC classification number: H04L25/03159 ,  H04L25/03019 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/085 ,  H04L2025/03681

Abstract: An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

Abstract translation: 集成电路对表示为一系列符号的数据信号进行均衡。 符号形成具有不同频率分量的数据模式。 通过考虑这些模式，集成电路可以对特定于频率分量的子集的均衡设置进行实验，从而找到优化均衡的均衡控制设置。 可以通过设置均衡器来最大化符号幅度来实现优化。

公开(公告)号：US09104646B2

公开(公告)日：2015-08-11

申请号：US14098322

申请日：2013-12-05

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Brent Haukness ,  Mehmet Günhan Ertosun ,  Ian P. Shaeffer

IPC: G11C11/00 ,  G06F11/20

CPC classification number: G06F11/2053 ,  G11C13/0002 ,  G11C13/0033 ,  G11C16/3431 ,  G11C29/50008 ,  G11C29/52 ,  G11C2029/0409

Abstract: Components of a memory system, such as a memory controller and memory device, which detect accumulated memory read disturbances and correct such disturbances before they reach a level that causes errors. The memory device includes a memory array and a disturbance control circuit. The memory array includes a plurality of memory rows. Each memory row is associated with a disturbance warning circuit having a state that corresponds to an accumulated disturbance in the memory row. The disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether the disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row. If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row to reduce the accumulated disturbances.

Abstract translation: 诸如存储器控制器和存储器件的存储器系统的组件，其在累积的存储器读出干扰之前检测累积的存储器读取干扰并且在达到导致错误的电平之前校正这种干扰。 存储器件包括存储器阵列和干扰控制电路。 存储器阵列包括多个存储器行。 每个存储器行与具有对应于存储器行中的累积干扰的状态的干扰警告电路相关联。 干扰控制电路响应于由行访问命令指定的多个存储行的存储器行的激活，基于与存储器相关联的干扰警告电路的状态来确定存储器行中是否存在干扰条件 行。 如果存在干扰条件，则扰动控制电路使得对存储器行进行恢复操作以减少累积的干扰。

公开(公告)号：US09098209B2

公开(公告)日：2015-08-04

申请号：US14064167

申请日：2013-10-27

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Vlad Fruchter ,  Lawrence Lai ,  Pradeep Batra ,  Steven C. Woo ,  Wayne Frederick Ellis

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0671 ,  G06F12/06 ,  G06F13/16 ,  G06F13/1621 ,  G06F13/1626 ,  G06F13/1668 ,  G11C7/10

Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.

Abstract translation: 通过存储器接口连接到存储器控制器的模块的存储器空间可以用作命令缓冲器。 模块通过命令缓冲区接收的命令由模块执行。 存储器控制器可以无序地写入命令缓冲器。 存储器控制器可能会延迟或消除对命令缓冲区的写入。 与命令关联的标签用于指定执行顺序命令。 模块的存储空间中的状态缓冲区用于通信是否接收或执行了命令。 通过状态缓冲器接收的信息可以用作确定将命令重新发送到命令缓冲区的基础。

公开(公告)号：US09094238B2

公开(公告)日：2015-07-28

申请号：US13216047

申请日：2011-08-23

Applicant: Jared L. Zerbe ,  Fred F. Chen ,  Andrew Ho ,  Ramin Farjad-Rad ,  John W. Poulton ,  Kevin S. Donnelly ,  Brian S. Leibowitz

Inventor： Jared L. Zerbe ,  Fred F. Chen ,  Andrew Ho ,  Ramin Farjad-Rad ,  John W. Poulton ,  Kevin S. Donnelly ,  Brian S. Leibowitz

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L27/01 ,  H04L1/00 ,  H04L7/033 ,  H04L25/03 ,  H04L25/497 ,  H04W52/20 ,  H04L7/00 ,  H04L25/02 ,  H04W52/22

CPC classification number: H04L27/01 ,  H04L1/0026 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/497 ,  H04L2025/03503 ,  H04W52/20 ,  H04W52/225 ,  Y02D70/00

Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

公开(公告)号：US09087572B2

公开(公告)日：2015-07-21

申请号：US14091213

申请日：2013-11-26

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Brent Steven Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G11C7/00 ,  G11C15/00 ,  G11C13/00 ,  G11C15/04

CPC classification number: G11C15/00 ,  G11C13/0002 ,  G11C15/046

Abstract: A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F2 depending on the number of layers of memory cells formed over the switching device.

Abstract translation: 内容可寻址存储器可以包括具有多个存储器元件（诸如RRAM元件）的存储器单元阵列，以存储基于多个电阻状态的数据。 诸如晶体管的公共开关器件可以在读，写，擦除和搜索操作期间用匹配线电耦合多个多个存储器元件。 在搜索操作中，存储器单元可以接收搜索词，并且基于由存储元件存储的数据和提供给存储器元件的搜索词来选择性地排放匹配线上的电压电平。 匹配线的电压电平可以指示搜索词是否匹配存储在存储单元中的数据。 内容可寻址存储器可能潜在地具有根据在开关器件上形成的存储器单元的层数在0.5F2下的有效存储单元大小。

公开(公告)号：US09087568B1

公开(公告)日：2015-07-21

申请号：US13848832

申请日：2013-03-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C8/00 ,  G11C8/18 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1039 ,  G11C7/222 ,  G11C11/40615 ,  G11C11/4076

Abstract: Chip selection and internal clocking functions are enabled within an integrated circuit memory component in response to a single “chip-enable” control signal, thus reducing memory system pin count and wiring complexity relative to designs that require separate chip-select and clock-enable signals. Internal clocking logic may also be provided to generate timing signal edges more precisely limited to the number required to complete a given memory component operation, reducing the number of unnecessary timing events and lowering power consumption. Further, internal read and write clock signals may be speculatively enabled within the memory component to more quickly stabilize those clocks in preparation for data transmission and reception operations, potentially lowering memory access latency.

Abstract translation: 芯片选择和内部时钟功能在集成电路存储器组件内响应于单个“芯片使能”控制信号而被使能，从而相对于需要单独的芯片选择和时钟使能信号的设计而减少存储器系统引脚数量和布线复杂度 。 还可以提供内部时钟逻辑以产生更精确地限制完成给定存储器组件操作所需的数量的定时信号边沿，减少不必要的定时事件的数量并降低功耗。 此外，内部读和写时钟信号可以在存储器组件内被推测启用，以更快地稳定这些时钟以准备数据传输和接收操作，潜在地降低存储器访问等待时间。

公开(公告)号：US09077575B2

公开(公告)日：2015-07-07

申请号：US13911363

申请日：2013-06-06

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract translation: 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

公开(公告)号：US20150177815A1

公开(公告)日：2015-06-25

申请号：US14416088

申请日：2013-09-06

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian Hing-Kit Tsang ,  Barry William Daly

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/28 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a START memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

Abstract translation: 所公开的实施例涉及支持动态突发以促进START存储器控制器和存储设备之间的频率敏捷通信的系统。 在操作期间，系统监视在存储器件和存储器控制器之间的接口处接收到的参考时钟信号。 在检测到从全速率到子速率的参考时钟信号中的频率变化时，接口以突发模式操作，其中数据通过由接口的部分断电的中间的低功率间隔分开的脉冲串传送。

公开(公告)号：US09054906B2

公开(公告)日：2015-06-09

申请号：US14159597

申请日：2014-01-21

Applicant: Robert E. Palmer

Inventor： Robert E. Palmer

IPC: H04L27/01 ,  H04L25/03 ,  H04L7/04 ,  H04L25/06

CPC classification number: H04L27/01 ,  H04L7/041 ,  H04L7/046 ,  H04L25/03006 ,  H04L25/03273 ,  H04L25/069

Abstract: An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.