公开(公告)号：US07215033B2

公开(公告)日：2007-05-08

申请号：US10899175

申请日：2004-07-27

Applicant: Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

Inventor： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected.

Abstract translation: 一种晶片级堆叠结构，包括包括第一芯片尺寸的至少一个第一器件芯片的第一晶片，其中每个第一器件芯片包含第一多个输入/输出（I / O）焊盘，第二晶片包括至少一个 第二芯片尺寸小于第一芯片尺寸的第二器件芯片，其中每个第二器件芯片包含第二多个I / O焊盘，其中所述至少一个第二器件芯片增加到所述第一芯片尺寸，其中所述第一晶片 并且第二晶片被堆叠，并且其中第一晶片和第二晶片彼此耦合。 一种形成晶片级堆叠结构的方法，包括形成包括第一芯片尺寸的至少一个第一器件芯片的第一晶片，其中每个第一器件芯片包含第一多个输入/输出（I / O）焊盘，形成 第二晶片，其包括小于第一芯片尺寸的第二芯片尺寸的至少一个第二器件芯片，其中每个第二器件芯片包含第二多个I / O焊盘，其中所述至少一个第二器件芯片增加到所述第一芯片 尺寸，堆叠第一晶片和第二晶片，并且将第一晶片和第二晶片彼此耦合。 一种系统级封装，包括晶片级堆叠结构，其包括具有第一多个输入/输出（I / O）焊盘的至少一个第一器件芯片和至少一个具有第二多个I / O焊盘的第二器件芯片 ，以及与晶片级堆叠结构连接的公共电路板。

公开(公告)号：US20070048969A1

公开(公告)日：2007-03-01

申请号：US11436851

申请日：2006-05-18

Applicant: Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-II Han

Inventor： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-II Han

IPC: H01L21/30

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/31 ,  H01L24/83 ,  H01L24/90 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/08112 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/81141 ,  H01L2224/83136 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05552

Abstract: In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with such voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete gap fill. In addition, mechanical reliability is improved, alleviating the problems associated with cracking and delamination, and leading to an improvement in device yield and device reliability.

Abstract translation: 在堆叠式芯片构造及其制造方法中，使用消除下部和上部切屑之间的空隙以及与这种空隙相关的裂纹和分层问题的相对简单的工艺，完全填充下部和上部切屑之间的间隙。 本发明可应用于芯片级接合和晶片级接合方式。 在堆叠芯片或堆叠晶片之前，将光敏聚合物层施加到第一芯片或晶片。 感光性聚合物层被部分固化，使得光敏聚合物层在结构上稳定，同时保持其粘合性能。 第二芯片或晶片被堆叠，对准并且结合到第一芯片或晶片，然后使光敏聚合物层固化以完全结合第一和​​第二芯片或晶片。 以这种方式，在提供完全的间隙填充的同时，大大提高了芯片/晶片之间的粘附。 此外，机械可靠性得到改善，减轻了与开裂和分层相关的问题，从而提高了设备​​的产量和设备的可靠性。

公开(公告)号：US20070045836A1

公开(公告)日：2007-03-01

申请号：US11436822

申请日：2006-05-18

Applicant: Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-Il Han ,  Dong-Ho Lee

Inventor： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-Il Han ,  Dong-Ho Lee

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/31 ,  H01L24/83 ,  H01L24/90 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/08112 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/81141 ,  H01L2224/83136 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05552

Abstract: In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower chip and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete fill of the gap. In addition, mechanical reliability is improved and CTE mismatch is reduced, alleviating the problems associated with warping, cracking and delamination, and leading to an improvement in device yield and device reliability.

Abstract translation: 在堆叠式芯片结构及其制造方法中，使用消除下部和上部芯片之间的空隙以及与空隙相关的开裂和分层问题的相对简单的工艺，完全填充下部芯片和上部芯片之间的间隙。 本发明可应用于芯片级接合和晶片级接合方式。 在堆叠芯片或堆叠晶片之前，将光敏聚合物层施加到第一芯片或晶片。 感光性聚合物层被部分固化，使得光敏聚合物层在结构上稳定，同时保持其粘合性能。 第二芯片或晶片被堆叠，对准并且结合到第一芯片或晶片，然后使光敏聚合物层固化以完全结合第一和​​第二芯片或晶片。 以这种方式，在提供间隙的完全填充的同时，大大提高了芯片/晶片之间的粘附。 另外，提高了机械可靠性，降低了CTE失配，缓解了翘曲，开裂，脱层等问题，提高了设备​​的产量和设备的可靠性。

公开(公告)号：US20070019089A1

公开(公告)日：2007-01-25

申请号：US11342799

申请日：2006-01-31

Applicant: Yong-Chai Kwon ,  Suk-Chae Kang ,  Kang-Wook Lee ,  Gu-Sung Kim ,  Jong-Woo Kim ,  Seong-II Han ,  Sun-Wook Heo ,  Jung-Hang Yi ,  Keum-Hee Ma

Inventor： Yong-Chai Kwon ,  Suk-Chae Kang ,  Kang-Wook Lee ,  Gu-Sung Kim ,  Jong-Woo Kim ,  Seong-II Han ,  Sun-Wook Heo ,  Jung-Hang Yi ,  Keum-Hee Ma

IPC: H04N5/335

CPC classification number: H04N5/2253 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/48095 ,  H01L2924/16235 ,  H01L2924/00014

Abstract: An image sensor device and methods thereof. In an example method, a protective layer may be formed over at least one microlens. An adhesive layer may be formed over the protective layer. The adhesive layer may be removed so as to expose the protective layer. The protective layer may be removed so as to expose the at least one microlens, the exposed at least one microlens not including residue from the adhesive layer. The at least one microlens may have an improved functionality due at least in part to the lack of residue from the adhesive layer. In an example, the at least one microlens may be included in an image sensor module.

Abstract translation: 一种图像传感器装置及其方法。 在示例性方法中，可以在至少一个微透镜上形成保护层。 可以在保护层上形成粘合剂层。 可以去除粘合剂层以暴露保护层。 可以去除保护层，以便露出至少一个微透镜，暴露的至少一个微透镜不包括来自粘合剂层的残留物。 由于至少部分地由于粘合剂层缺乏残留物而使至少一个微透镜具有改进的功能。 在一个示例中，至少一个微透镜可以包括在图像传感器模块中。

公开(公告)号：US07119425B2

公开(公告)日：2006-10-10

申请号：US11089361

申请日：2005-03-25

Applicant: Se-Young Jeong ,  Kang-Wook Lee

Inventor： Se-Young Jeong ,  Kang-Wook Lee

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11 ,  H01L2224/1146 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/81 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The chip package includes a first and second semiconductor chip. The first semiconductor chip has a first connection structure that electrically connects to a bond pad on a first surface of the first semiconductor chip. The second semiconductor chip has a second connection structure. The second connection structure is electrically connected to a bond pad on a first surface of the second semiconductor chip and extends through the second semiconductor chip to a second surface of the second semiconductor chip. A portion of the second connection structure extending to the second surface of the second semiconductor chip is electrically connected to the first connection structure and formed of a harder material than the first connection structure.

Abstract translation: 芯片封装包括第一和第二半导体芯片。 第一半导体芯片具有电连接到第一半导体芯片的第一表面上的接合焊盘的第一连接结构。 第二半导体芯片具有第二连接结构。 第二连接结构电连接到第二半导体芯片的第一表面上的接合焊盘，并且延伸穿过第二半导体芯片到第二半导体芯片的第二表面。 延伸到第二半导体芯片的第二表面的第二连接结构的一部分电连接到第一连接结构，并且由比第一连接结构更硬的材料形成。

公开(公告)号：US20060152615A1

公开(公告)日：2006-07-13

申请号：US11149298

申请日：2005-06-10

Applicant: Yong-Chai Kwon ,  Kang-Wook Lee ,  Gu-Sung Kim ,  Keum-Hee Ma ,  Seong-Il Han

Inventor： Yong-Chai Kwon ,  Kang-Wook Lee ,  Gu-Sung Kim ,  Keum-Hee Ma ,  Seong-Il Han

IPC: H04N5/225

CPC classification number: H01L27/14618 ,  H01L24/48 ,  H01L24/49 ,  H01L27/14625 ,  H01L27/14634 ,  H01L27/14685 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/16235 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An assembly may include a wafer and a plate may be mounted on the wafer. The wafer may have image sensor chips and scribe lines demarcating each image sensor chip. The image sensor chip may include an active surface. Chip pads and a micro-lens may be provided on the active surface. A photo-sensitive adhesive pattern may be provided between the plate and a region of the active surface between the chip pads and the micro-lens. An image sensor device implementing an image sensor chip having an individual plate may also be provided.

Abstract translation: 组件可以包括晶片，并且板可以安装在晶片上。 晶片可以具有划分每个图像传感器芯片的图像传感器芯片和划线。 图像传感器芯片可以包括有源表面。 芯片焊盘和微透镜可以设置在有源表面上。 可以在平板与芯片垫和微透镜之间的活性表面的区域之间设置光敏粘合剂图案。 还可以提供实现具有单独板的图像传感器芯片的图像传感器装置。

公开(公告)号：US20050164483A1

公开(公告)日：2005-07-28

申请号：US10922172

申请日：2004-08-20

Applicant: Se-Young Jeong ,  Jin-Hak Choi ,  Nam-Seog Kim ,  Kang-Wook Lee

Inventor： Se-Young Jeong ,  Jin-Hak Choi ,  Nam-Seog Kim ,  Kang-Wook Lee

IPC: H01L21/44 ,  H01L21/50 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L24/11 ,  H01L24/02 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  Y10S438/951 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method of forming a solder bump may involve forming a first photoresist pattern on a wafer having a pad. The first photoresist pattern may have an opening that exposes a portion of the pad. A first under bump metallurgy (UBM) layer may be formed on the pad, and a second UBM layer may be formed on the first photoresist pattern. A second photoresist pattern may be formed that exposes the first UBM layer and covers the second UBM layer. A solder bump may be formed in the opening. The second photoresist pattern and the first photoresist pattern may be removed using a stripper, thereby removing the second UBM layer by a lift-off method.

Abstract translation: 形成焊料凸点的方法可以包括在具有焊盘的晶片上形成第一光致抗蚀剂图案。 第一光致抗蚀剂图案可以具有露出垫的一部分的开口。 可以在焊盘上形成第一凸点下冶金（UBM）层，并且可以在第一光致抗蚀剂图案上形成第二UBM层。 可以形成第二光致抗蚀剂图案，其暴露第一UBM层并覆盖第二UBM层。 可以在开口中形成焊料凸块。 可以使用剥离剂除去第二光致抗蚀剂图案和第一光致抗蚀剂图案，从而通过剥离方法去除第二UBM层。

公开(公告)号：US20050046002A1

公开(公告)日：2005-03-03

申请号：US10890995

申请日：2004-07-15

Applicant: Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

Inventor： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/98 ,  H01L23/48 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/44 ,  H01L21/48 ,  H01L23/02

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

Abstract translation: 通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。 然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。 除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。 优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率 并提高产量。

公开(公告)号：US5756146A

公开(公告)日：1998-05-26

申请号：US815826

申请日：1997-03-12

Applicant: Kang-Wook Lee ,  Alfred Viehbeck

Inventor： Kang-Wook Lee ,  Alfred Viehbeck

IPC: G01N21/95 ,  H05K1/02 ,  H05K3/24 ,  H05K3/46 ,  H05H1/00

CPC classification number: G01N21/95 ,  H05K1/0269 ,  H05K2203/072 ,  H05K2203/161 ,  H05K3/244 ,  H05K3/4644

Abstract: Copper lines or molybdenum lines on a substrate are inspected for defects by coating a metallized substrate with an inspection layer followed by imaging the substrate, and removing the inspection layer after the imaging. The inspection layer can be a light reflecting metal or a combination of a light reflecting metal and light-absorbing organic compound.

Abstract translation: 通过用检查层涂覆金属化基板，然后对基板进行成像来检查基板上的铜线或钼线，并在成像之后移除检查层。 检查层可以是光反射金属或光反射金属和光吸收有机化合物的组合。

公开(公告)号：US5582858A

公开(公告)日：1996-12-10

申请号：US474985

申请日：1995-06-07

Applicant: Eleftherios Adamopoulos ,  Jungihl Kim ,  Kang-Wook Lee ,  Tae S. Oh ,  Terrence R. O'Toole ,  Sampath Purushothaman ,  John J. Ritsko ,  Jane M. Shaw ,  Alfred Viehbeck ,  George F. Walker

Inventor： Eleftherios Adamopoulos ,  Jungihl Kim ,  Kang-Wook Lee ,  Tae S. Oh ,  Terrence R. O'Toole ,  Sampath Purushothaman ,  John J. Ritsko ,  Jane M. Shaw ,  Alfred Viehbeck ,  George F. Walker

IPC: B32B7/10 ,  B32B15/08 ,  B32B15/088 ,  B32B27/00 ,  C08G73/00 ,  C08G73/10 ,  H01B3/30 ,  H01L21/52 ,  H05K1/03 ,  H05K3/46 ,  B05D5/10

CPC classification number: C08G73/1089 ,  C08G73/1003 ,  C08G73/1007 ,  C08G73/101 ,  H01B3/306 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/31721

Abstract: The disclosure describes a multilayer article of manufacture comprising a substrate having adhered to it a terminally unsaturated adhesive polyimide, where the surface of the adhesive opposite the substrate is adhered to a polyimide, the article further characterized in having one set or a plurality of alternating layers of the terminally unsaturated adhesive polyimide and the polyimide. In another embodiment, the article has at least one adhesive polyimide layer adhered to a metal substrate or an electrical circuit component such as an integrated circuit, or means for forming electrical connections in an electrical circuit such as metal conduits on the circuit or a wiring network embedded within a ceramic and/or polymer substrate.In manufacturing the article of manufacture, a surface treatment technique such as wet process or a plasma/optional silane coupling agent may be applied to either the substrate, adhesive polyimide film or polyimide film prior to the bonding operation.A novel adhesive polyimide is also described which is an adhesive polyimide such as ODPA-APB terminated with unsaturated heterocyclic monoamines such as azaadenines, aminobenzotriazoles, aminopurines or aminopyrazolopyrimidines and optionally anhydrides, aminoacetylenes, vinylamines or amino phosphines. The novel polyimide may also contain unsaturated heterocyclic groups in the polymer backbone or chain, either as a partial or complete replacement for the aromatic diamines used in synthesizing the polyimide. This novel adhesive polyimide in this invention acts as an adhesive layer for the polymer-substrate (copper, polymer, glass ceramic) interface as well as a copper diffusion barrier layer for the polymer-copper interface.

Abstract translation: 本公开描述了一种多层制品，其包括粘附到其上的末端不饱和粘合聚酰亚胺的基底，其中与基底相对的粘合剂的表面粘附到聚酰亚胺上，该制品进一步的特征在于具有一组或多个交替层 的末端不饱和粘合聚酰亚胺和聚酰亚胺。 在另一个实施方案中，制品具有粘附到金属基底或诸如集成电路的电路部件的至少一个粘合聚酰亚胺层，或用于在电路中形成电连接的装置，例如电路上的金属管道或布线网络 嵌入在陶瓷和/或聚合物基材内。 在制造该制品时，可以在接合操作之前将表面处理技术如湿法或等离子体/任选的硅烷偶联剂施加到基底，粘合聚酰亚胺膜或聚酰亚胺膜上。 还描述了一种新型粘合聚酰亚胺，其是粘合聚酰亚胺，例如用不饱和杂环单胺如氮杂腺嘌呤，氨基苯并三唑，氨基嘌呤或氨基吡唑并嘧啶和任选的酸酐，氨基乙炔，乙烯胺或氨基膦封端的ODPA-APB。 新型聚酰亚胺还可以在聚合物主链或链中含有不饱和杂环基团，作为用于合成聚酰亚胺的芳族二胺的部分或完全替代物。 本发明中的这种新型粘合聚酰亚胺作为聚合物基材（铜，聚合物，玻璃陶瓷）界面的粘合剂层以及用于聚合物 - 铜界面的铜扩散阻挡层。