公开(公告)号：US20050184368A1

公开(公告)日：2005-08-25

申请号：US11112109

申请日：2005-04-21

申请人： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

公开(公告)号：US06884652B2

公开(公告)日：2005-04-26

申请号：US10420427

申请日：2003-04-22

申请人： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/48 ,  H01L21/68 ,  H01L23/31 ,  H01L21/44 ,  H01L21/50

CPC分类号： H01L21/4832 ,  H01L21/4857 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

公开(公告)号：US06819565B2

公开(公告)日：2004-11-16

申请号：US10341711

申请日：2003-01-14

申请人： Nai-Hao Kao ,  Yu-Po Wang ,  Wen-Jung Chiang

发明人： Nai-Hao Kao ,  Yu-Po Wang ,  Wen-Jung Chiang

IPC分类号： H05K720

CPC分类号： H01L23/36 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85413 ,  H01L2224/85444 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A cavity-down ball grid array (CDBGA) semiconductor package with a heat spreader is provided, in which a substrate is formed with at least a ground ring, a plurality of ground vias, a ground layer, and at least an opening for receiving at least a chip. The substrate is mounted in a cavity of the heat spreader, and an electrically conductive adhesive is disposed between an inner wall of the cavity and edges of the substrate, so as to allow the ground layer and the ground ring exposed to the edges of the substrate to be electrically connected to the heat spreader by means of the electrically conductive adhesive. By the above arrangement with the heat spreader being included in a grounding circuit path of the chip, ground floatation and excess ground inductance and resistance can be prevented for the semiconductor package, thereby solving heat-dissipation, electromagnetic interference and crosstalk problems.

摘要翻译： 提供了具有散热器的空腔向下球栅阵列（CDBGA）半导体封装，其中衬底形成有至少接地环，多个接地通孔，接地层和至少一个开口，用于在 最小的芯片 基板安装在散热器的空腔中，并且导电粘合剂设置在空腔的内壁和基板的边缘之间，以便使接地层和接地环暴露于基板的边缘 通过导电粘合剂与散热器电连接。 通过上述布置，散热器被包括在芯片的接地电路中，可以防止半导体封装的地面漂浮和多余的接地电感和电阻，从而解决散热，电磁干扰和串扰问题。

公开(公告)号：US07939383B2

公开(公告)日：2011-05-10

申请号：US11928708

申请日：2007-10-30

申请人： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/00

CPC分类号： H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/58 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K3/007 ,  H05K3/3457 ,  H05K3/4682 ,  H05K2203/0152 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

摘要翻译： 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US20100297842A1

公开(公告)日：2010-11-25

申请号：US12851971

申请日：2010-08-06

申请人： Chun Chi KE ,  Chien-Ping HUANG ,  Don-Son JIUNG ,  Yu-Po WANG

发明人： Chun Chi KE ,  Chien-Ping HUANG ,  Don-Son JIUNG ,  Yu-Po WANG

IPC分类号： H01L21/60

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A conductive bump structure for a semiconductor device and a method for fabricating the same are provided. A metal bump is formed on an under bump metallurgy (UBM) structure electrically connected to and formed on a connection pad of the semiconductor device, wherein the metal bump is sized smaller than the UBM structure. Subsequently, a solder bump is mounted on the UBM structure and encapsulates the metal bump, so as to increase the bonding area and simultaneously allow the solder bump to be sufficiently wetted on the UBM structure to enhance bonding stress of the solder bump.

摘要翻译： 提供了一种用于半导体器件的导电凸块结构及其制造方法。 金属凸块形成在电连接到半导体器件的连接焊盘上并形成在半导体器件的连接焊盘上的凸块下冶金（UBM）结构上，其中金属凸块的尺寸小于UBM结构。 随后，在UBM结构上安装焊料凸点并封装金属凸块，以便增加接合面积，并同时允许焊料凸块在UBM结构上充分润湿以增强焊料凸块的粘结应力。

公开(公告)号：US07808110B2

公开(公告)日：2010-10-05

申请号：US12011906

申请日：2008-01-30

申请人： Yu-Po Wang ,  Chien-Ping Huang ,  Wei-Chun Lin ,  Wen Cheng Lee

发明人： Yu-Po Wang ,  Chien-Ping Huang ,  Wei-Chun Lin ,  Wen Cheng Lee

IPC分类号： H01L29/40

CPC分类号： H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor package substrate proposed by the invention includes a base body and a plurality of finger pads disposed on surface of the base body, wherein the finger pads are arranged in such a way that an angle is formed between connecting line of centers of two adjacent finger pads and the direction in which the finger pads are arranged. The finger pads are waterdrop shaped finger pads with arc ends and angle ends alternately disposed on surface of the substrate, alternately disposed waterdrop shaped finger pads and arc shaped finger pads, or alternately disposed arc shaped finger pads at a predetermined spacing. According to the present invention, distance between adjacent finger pads is reduced and problem of short circuit as a result of erroneous contact between bonding wire and adjacent finger pad is prevented.

摘要翻译： 本发明提出的半导体封装基板包括基体和设置在基体表面上的多个指垫，其中指垫以这样一种方式布置，使得两个相邻手指的中心的连接线之间形成一角度 垫和指垫的排列方向。 手指垫是具有弧端的水滴状指垫，并且角度端交替地设置在基板的表面上，交替地设置水滴形指状垫和弧形指状垫，或者以预定间隔交替布置的圆弧形指垫。 根据本发明，相邻指垫之间的距离减小，并且防止了接合线和相邻指垫之间的错误接触的结果导致的短路问题。

公开(公告)号：US20080277786A1

公开(公告)日：2008-11-13

申请号：US12156874

申请日：2008-06-05

申请人： Chun-Lung Chen ,  Yu-Po Wang ,  Jeng-Yuan Lai ,  Cheng-Hsu Hsiao

发明人： Chun-Lung Chen ,  Yu-Po Wang ,  Jeng-Yuan Lai ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/48

CPC分类号： H05K1/115 ,  H01L23/3677 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0206 ,  H05K1/112 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2201/10674 ,  H01L2224/0401

摘要： A semiconductor package substrate includes a body having an upper surface and a lower surface opposite to one another, a plurality of circuit layers formed in the body, a plurality of solder pads formed on the upper surface of the body, and a plurality of solder ball pads formed on the lower surface of the body. Each of the solder pads is electrically connected to one of the solder ball pads via the circuit layers and conductive structures disposed between the circuit layers, wherein the circuit layers and conductive structures are configured to expand outwardly in a fan-out manner so as to provide more space between the circuit layers closer to the lower surface of the body such that part of the solder pad-solder ball pad electrical connections can comprise a plurality of parallel connected conductive structures formed in the space, thereby enhancing the heat conducting passageway and the effect of heat-dissipation without having to dispose more solder pads on surface of the substrate.

摘要翻译： 半导体封装基板包括具有彼此相对的上表面和下表面的主体，形成在主体中的多个电路层，形成在主体的上表面上的多个焊盘，以及多个焊球 衬垫形成在身体的下表面上。 每个焊盘通过设置在电路层之间的电路层和导电结构电连接到焊球之一，其中电路层和导电结构被配置为以扇出方式向外扩展，以便提供 电路层之间的距离更靠近主体的下表面的空间更多，使得焊料焊盘 - 焊球焊盘电连接的一部分可以包括形成在该空间中的多个平行连接的导电结构，从而增强导热通道和效果 的散热而不必在基板的表面上设置更多的焊盘。

公开(公告)号：US20080150128A1

公开(公告)日：2008-06-26

申请号：US12004779

申请日：2007-12-21

申请人： Liang-Yi Hung ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

发明人： Liang-Yi Hung ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/34 ,  H01L21/02

CPC分类号： H01L23/42 ,  H01L23/3128 ,  H01L23/36 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/838 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/3512

摘要： A heat dissipating chip structure and a fabrication method thereof and a package having the same are provided. The fabrication method mainly includes: forming a metal layer on an non-active surface of a wafer having a plurality of chips with the metal layer thereof providing a better solder bonding with a thermal interface material at positions corresponding to centers of each chips, and not being disposed on the cutting paths between the chips to prevent crack and peel off during the cutting. Further, when the chips are subsequently mounted on a chip carrier and further attached to a heat dissipating sheet with another metal layer on a surface thereof with the thermal interface material (TIM), with different surface areas of the metal layers formed on the heat dissipating sheet and the chip, an inward and downward force is generated in the TIM to limit an wetting area.

摘要翻译： 散热芯片结构及其制造方法以及具有该散热芯片的封装。 该制造方法主要包括：在具有多个芯片的晶片的非活性表面上形成金属层，其金属层与对应于每个芯片的中心的位置处的热界面材料提供更好的焊接，而不是 设置在切屑之间的切割路径上，以防止切割期间的裂纹和剥离。 此外，当芯片随后安装在芯片载体上并且进一步连接到具有热界面材料（TIM）的表面上的另一金属层的散热片时，在散热片上形成的金属层的不同表面积 片材和芯片，TIM中产生向内和向下的力以限制润湿区域。

公开(公告)号：US20080088011A1

公开(公告)日：2008-04-17

申请号：US11974441

申请日：2007-10-12

申请人： Han-Ping Hu ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

发明人： Han-Ping Hu ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/49 ,  H01L21/58

CPC分类号： H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16151 ,  H01L2924/16195 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor package on which a semiconductor device can be stacked and fabrication method thereof are provided. The fabrication method includes the steps of mounting and electrically connecting at least one semiconductor chip on the substrate, mounting an electrical connecting structure consisting of an upper layer circuit board and a lower layer circuit board on the substrate and electrically connecting the electrical connecting structure to the substrate, where the semiconductor chip is received in a receiving space formed in the electrical connecting structure; forming an encapsulant on the substrate encapsulating the semiconductor chip and the electrical connecting structure, and after the encapsulant is formed, exposing top surface of the upper layer circuit board with a plurality of solder pads from the encapsulant to allow at least one semiconductor device to electrically connect the upper layer circuit board so as to form a stack structure.

摘要翻译： 提供半导体器件可堆叠的半导体封装件及其制造方法。 该制造方法包括以下步骤：在基板上安装和电连接至少一个半导体芯片，将由上层电路板和下层电路板组成的电连接结构安装在基板上，并将电连接结构电连接到 衬底，其中所述半导体芯片被容纳在形成在所述电连接结构中的接收空间中; 在封装半导体芯片和电连接结构的基板上形成密封剂，并且在形成密封剂之后，用来自密封剂的多个焊盘将上层电路板的顶表面曝光，以允许至少一个半导体器件电 连接上层电路板，形成堆叠结构。

公开(公告)号：US20070181990A1

公开(公告)日：2007-08-09

申请号：US11591974

申请日：2006-11-01

申请人： Chien-Ping Huang ,  Chih-Ming Huang ,  Han-Ping Pu ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

发明人： Chien-Ping Huang ,  Chih-Ming Huang ,  Han-Ping Pu ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L23/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.

摘要翻译： 提供了堆叠半导体结构及其制造方法。 该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面， 经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板， 接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。 本发明防止回流引起的污染，备有特殊的模具，并消除闪光。