公开(公告)号：US4261004A

公开(公告)日：1981-04-07

申请号：US929959

申请日：1978-08-01

申请人： Toshiaki Masuhara ,  Osamu Minato ,  Yoshio Sakai ,  Toshio Sasaki ,  Masaharu Kubo ,  Kotaro Nishimura ,  Tokumasa Yasui

发明人： Toshiaki Masuhara ,  Osamu Minato ,  Yoshio Sakai ,  Toshio Sasaki ,  Masaharu Kubo ,  Kotaro Nishimura ,  Tokumasa Yasui

IPC分类号： H03F1/52 ,  H01L21/02 ,  H01L21/822 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/78 ,  H03F1/42

CPC分类号： H01L28/20 ,  H01L27/0251 ,  H01L27/0288

摘要： On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K.OMEGA./.quadrature. and a second polycrystalline silicon member having a resistivity lower than 1 K.OMEGA./.quadrature. and being maintained at a fixed potential. This second polycrystalline silicon member faces at least a part of the first silicon member with polycrystalline silicon of a resistivity higher than 100 K.OMEGA./.quadrature. interposed therebetween. The input terminal of the first polycrystalline silicon member is connected to an input pad of the MOS type semiconductor device to be protected and the output terminal of the first polycrystalline silicon member is connected to an input gate of the semiconductor device to be protected. The input gate of the semiconductor device is protected by utilizing the punch-through effect in the interior of the polycrystalline silicon having a resistivity higher than 100 K.OMEGA./.quadrature..

摘要翻译： 在形成有要形成有待保护的MOS型半导体器件的半导体衬底的表面上的绝缘膜的表面上形成有具有输入和输出端子的电阻率低于1KΩ的第一多晶硅元件， 并且具有电阻率低于1KΩ/□并且保持在固定电位的第二多晶硅部件。 该第二多晶硅部件面对第一硅部件的至少一部分，其中多晶硅的电阻率高于100KΩ，并插入其间。 第一多晶硅部件的输入端子连接到要被保护的MOS型半导体器件的输入焊盘，并且第一多晶硅部件的输出端子连接到待保护的半导体器件的输入栅极。 半导体器件的输入栅极通过利用电阻率高于100KΩ/□的多晶硅的内部的穿透效应来保护。

公开(公告)号：US4223330A

公开(公告)日：1980-09-16

申请号：US5567

申请日：1979-01-22

申请人： Norio Koike ,  Iwao Takemoto ,  Shinya Ohba ,  Masaharu Kubo ,  Shuhei Tanaka

发明人： Norio Koike ,  Iwao Takemoto ,  Shinya Ohba ,  Masaharu Kubo ,  Shuhei Tanaka

IPC分类号： H01L27/146 ,  H04N5/335 ,  H04N5/359 ,  H04N5/374 ,  H01L27/14 ,  H01L29/78

CPC分类号： H01L27/14654

摘要： In a solid-state imaging device having, in one major surface region of a semiconductor substrate, photoelectric conversion elements which are disposed in a two-dimensional array, vertical switching metal-insulator-semiconductor field effect transistors and horizontal switching metal-insulator-semiconductor field effect transistors which select the photoelectric conversion elements, and vertical and horizontal scanning circuits which turn the switching transistors "on" and "off," a solid-state imaging device characterized in that the vertical switching metal-insulator-semiconductor field effect transistors which are not selected are placed into a deeper cutoff state, i.e., the major surface regions of the semiconductor substrate corresponding to gate electrodes of these vertical switching metal-insulator-semiconductor field effect transistors are placed at an accumulation level.

摘要翻译： 在具有在半导体衬底的一个主表面区域中设置为二维阵列的光电转换元件的立体成像器件中，垂直开关金属 - 绝缘体 - 半导体场效应晶体管和水平开关金属 - 绝缘体半导体 选择光电转换元件的场效应晶体管以及使开关晶体管“导通”和“截止”的垂直和水平扫描电路，其特征在于垂直开关金属 - 绝缘体半导体场效应晶体管 未选择的位置被置于更深的截止状态，即，对应于这些垂直开关金属 - 绝缘体 - 半导体场效应晶体管的栅极的半导体衬底的主表面区域被放置在累积水平。

公开(公告)号：US4132997A

公开(公告)日：1979-01-02

申请号：US764428

申请日：1977-01-31

申请人： Hiroo Masuda ,  Masaharu Kubo ,  Ryoichi Hori

发明人： Hiroo Masuda ,  Masaharu Kubo ,  Ryoichi Hori

IPC分类号： H01L29/10 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L29/1087

摘要： A MOS type field effect transistor has an electrode, which is in the neighborhood of, but not in contact with, the drain diffusion region and is electrically connected with the surface portion of the semiconductor substrate in which the MOS type field effect transistor is formed, and whose potential is held at the rear surface potential of the semiconductor substrate, i. e., the substrate bias potential.

公开(公告)号：US4011581A

公开(公告)日：1977-03-08

申请号：US68973

申请日：1970-09-02

申请人： Masaharu Kubo ,  Minoru Nagata ,  Yasunobu Kosa

发明人： Masaharu Kubo ,  Minoru Nagata ,  Yasunobu Kosa

IPC分类号： H01L29/78 ,  H01L21/76 ,  H01L23/29 ,  H01L27/02 ,  H01L27/092 ,  H01L29/00 ,  H01L29/06 ,  H01L27/04

CPC分类号： H01L29/0638 ,  H01L23/291 ,  H01L27/0251 ,  H01L27/0927 ,  H01L29/00 ,  H01L2924/0002 ,  H01L2924/13091

摘要： A semiconductor device which is provided, for the purpose of eliminating parasitic MOSFETs formed between at least two circuit elements (such as MOSFET, TRANSISTOR, RESISTOR, and the like) on a semiconductor substrate, with a high impurity concentration layer of the same conduction type as the substrate in a manner such that the layer is not only in the semiconductor substrate between said circuit elements but is also partially overlapped by the circuit element regions.

摘要翻译： 为了消除形成在半导体衬底上的至少两个电路元件（例如MOSFET，晶体管，电阻等）之间的寄生MOSFET，提供了具有相同导电类型的高杂质浓度层的半导体器件 作为基板，使得该层不仅在所述电路元件之间的半导体基板中，而且也部分地与电路元件区域重叠。

公开(公告)号：US07323771B2

公开(公告)日：2008-01-29

申请号：US11475936

申请日：2006-06-28

申请人： Ryo Fujita ,  Osamu Kubo ,  Kouki Noguchi ,  Masaharu Kubo ,  Michihiro Mishima ,  Yasuhiko Takahashi

发明人： Ryo Fujita ,  Osamu Kubo ,  Kouki Noguchi ,  Masaharu Kubo ,  Michihiro Mishima ,  Yasuhiko Takahashi

IPC分类号： H01L23/52

CPC分类号： G06F11/261 ,  G06F11/267 ,  G06F15/7867 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

公开(公告)号：US07158817B2

公开(公告)日：2007-01-02

申请号：US11296316

申请日：2005-12-08

申请人： Masaharu Kubo

发明人： Masaharu Kubo

IPC分类号： H04M1/00

CPC分类号： G06F1/1624 ,  G06F1/1616 ,  G06F1/1647 ,  G06F1/1671 ,  H04M1/0214 ,  H04M1/0235 ,  H04M15/30 ,  H04M15/41 ,  H04M15/56 ,  H04M15/82 ,  H04M2215/0164 ,  H04M2215/202 ,  H04M2215/2026 ,  H04M2215/32 ,  H04M2215/78 ,  H04W4/24 ,  H04W88/02 ,  Y10T16/5387

摘要： This portable terminal comprises, a first panel at least having a display, a second panel at least having a keyboard and a hinge unit attached on both the first panel and the second panel, wherein the hinge unit comprises both rotating mechanism around a center axis of said hinge unit and sliding mechanism in the longitudinal direction along the center axis of the hinge unit. The panels are electrically connected by interconnection scheme having both sliding contacts and rotating contacts. The scheme saving net numbers of keys is realized by the introduction of a convertible key concept corresponding to state of either that the portable terminal is used in a slid form as a wireless voice telephone or that it is used in a rotated form as a terminal making text data like a personal computer.

摘要翻译： 该便携式终端包括：至少具有显示器的第一面板，至少具有键盘的第二面板和附接在第一面板和第二面板上的铰链单元，其中铰链单元包括围绕中心轴线的旋转机构 所述铰链单元和滑动机构沿着铰链单元的中心轴在纵向方向上。 面板通过具有滑动触点和旋转触点的互连方案电连接。 通过引入与便携式终端以滑动形式用作无线语音电话或将其以旋转形式用作终端制造的状态的可转换键概念的实现，实现了节省网络数量的方案 文字数据，如个人电脑。

公开(公告)号：US20060237835A1

公开(公告)日：2006-10-26

申请号：US11475961

申请日：2006-06-28

申请人： Ryo Fujita ,  Osamu Kubo ,  Kouki Noguchi ,  Masaharu Kubo ,  Michihiro Mishima ,  Yasuhiko Takahashi

发明人： Ryo Fujita ,  Osamu Kubo ,  Kouki Noguchi ,  Masaharu Kubo ,  Michihiro Mishima ,  Yasuhiko Takahashi

IPC分类号： H01L23/52

CPC分类号： G06F11/261 ,  G06F11/267 ,  G06F15/7867 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

公开(公告)号：US07040011B2

公开(公告)日：2006-05-09

申请号：US10045036

申请日：2002-01-15

申请人： Toshihiko Tanaka ,  Masaharu Kubo ,  Takashi Hattori

发明人： Toshihiko Tanaka ,  Masaharu Kubo ,  Takashi Hattori

IPC分类号： H05K3/30

CPC分类号： G03F1/56 ,  H01L21/4867 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3025 ,  H05K3/0002 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring substrate is manufactured in short TAT.Wirings of the wiring substrate are formed by an exposure treatment using a photomask which has shade patterns each containing at least nano particles and a binder.

公开(公告)号：US06989600B2

公开(公告)日：2006-01-24

申请号：US10240651

申请日：2001-03-30

申请人： Masaharu Kubo ,  Ichiro Anjo ,  Akira Nagai ,  Osamu Kubo ,  Hiromi Abe ,  Hitoshi Akamine

发明人： Masaharu Kubo ,  Ichiro Anjo ,  Akira Nagai ,  Osamu Kubo ,  Hiromi Abe ,  Hitoshi Akamine

IPC分类号： H01L23/48

CPC分类号： H01L24/12 ,  H01L21/76838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01044 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014

摘要： CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel MISFET's (Qp) and a first-layer wiring (11) to a third-layer (13) formed on a main surface of a silicon substrate (1), and as another part, a fourth-layer wiring (14) to a seventh-layer wiring (17) formed on a main surface of a glass substrate (30) different from the silicon substrate (1). The main surface of the silicon substrate (1) and the main surface of the glass substrate (30) are arranged in face-to-face relation with each other, and a plurality of microbumps (20A) formed at the uppermost portion of the silicon substrate (1) and a plurality of microbumps (20B) formed at the uppermost portion of the glass substrate (30) are electrically connected, thereby constituting the CMOS logic LSI as a whole.

摘要翻译： CMOS逻辑LSI的一部分包括形成在硅的主表面上的n沟道MISFET（Qn），p沟道MISFET（Qp）和第一层布线（11）到第三层（13） 基板（1），另一部分形成在与硅基板（1）不同的玻璃基板（30）的主面上形成的第七层布线（17）。 硅基板（1）的主表面和玻璃基板（30）的主表面彼此面对面地布置，并且形成在所述玻璃基板的最上部的多个微丸（20A） 硅基板（1）和形成在玻璃基板（30）的最上部的多个微胶片（20A）电连接，从而构成整体上的CMOS逻辑LSI。

公开(公告)号：US06862220B2

公开(公告)日：2005-03-01

申请号：US10886725

申请日：2004-07-09

申请人： Takayuki Kawahara ,  Nozomu Matsuzaki ,  Terumi Sawase ,  Masaharu Kubo

发明人： Takayuki Kawahara ,  Nozomu Matsuzaki ,  Terumi Sawase ,  Masaharu Kubo

IPC分类号： G11C16/04 ,  G06F15/78 ,  H01L21/28 ,  H01L21/82 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H03K19/173

CPC分类号： H01L29/792 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/7885

摘要： A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.

摘要翻译： 包括安装在芯片上的非易失性存储单元和可变逻辑单元的半导体器件被配置为在较低电压下实现更高速度的操作。 半导体器件包括：非易失性存储器单元，其包括多个可重写非易失性存储器单元，以及根据要加载到其存储单元中的逻辑构造定义数据确定其逻辑功能的可变逻辑单元。 非易失性存储单元基本上具有由选择MOS晶体管和存储器MOS晶体管构成的分离栅极结构，并且被构造成使得选择MOS晶体管的栅极的介电耐受电压低于存储器MOS晶体管或栅极绝缘 选择MOS晶体管的层比耐高压MOS晶体管薄。 由于选择MOS晶体管具有高Gm，因此可以获得足够大的读取电流。