公开(公告)号：US07157791B1

公开(公告)日：2007-01-02

申请号：US10866393

申请日：2004-06-11

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L23/04

CPC classification number: H01L21/486 ,  H01L21/4832 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0134 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a pillar and a routing line, and a ground plane. The pillar is press-fit into an opening in the ground plane, and the ground plane is electrically connected to the pad.

Abstract translation: 半导体芯片组件包括包括导电焊盘，包括支柱和布线线的导电迹线以及接地平面的半导体芯片。 支柱被压配合到接地平面中的开口中，并且接地平面电连接到垫。

公开(公告)号：US07064012B1

公开(公告)日：2006-06-20

申请号：US10889368

申请日：2004-07-12

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L21/48

CPC classification number: H01L21/486 ,  H01L21/4832 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0134 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A method of making a semiconductor chip assembly includes providing a metal base that includes a metal plate and a metal layer, providing a routing line that contacts the metal layer and an etch mask that contacts the metal plate, providing a semiconductor chip that includes a conductive pad, mechanically attaching the chip to the routing line, electrically connecting the routing line to the pad, and etching the metal base using a first wet chemical that is selective of the metal plate and then a second wet chemical etch that is selective of the metal layer and the etch mask to form a pillar from an unetched portion of the metal base that contacts the routing line.

Abstract translation: 制造半导体芯片组件的方法包括提供包括金属板和金属层的金属基底，提供接触金属层的路由线和与金属板接触的蚀刻掩模，提供包括导电的半导体芯片 衬垫，将芯片机械地附接到布线线路，将布线线电连接到衬垫，以及使用对金属板有选择性的第一湿化学品，然后对金属选择性的第二湿化学蚀刻来蚀刻金属基底 层和蚀刻掩模，以从接触路线的金属基底的未蚀刻部分形成柱。

公开(公告)号：US06984576B1

公开(公告)日：2006-01-10

申请号：US10356800

申请日：2003-02-01

Applicant: Charles W. C. Lin ,  Cheng-Lien Chiang

Inventor： Charles W. C. Lin ,  Cheng-Lien Chiang

IPC: H01L21/44

CPC classification number: H01L23/5389 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/11474 ,  H01L2224/12 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H05K3/4046 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/00012

Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a metal base, an insulative base, a routing line and an interconnect, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, the routing line is disposed on a side of the insulative base that faces towards the chip, and the interconnect extends through a via in the insulative base and electrically connects the metal base and the routing line, forming an opening that extends through the insulative base and exposes the pad, forming a connection joint that electrically connects the routing line and the pad, and etching the metal base such that an unetched portion of the metal base forms a pillar that overlaps and is aligned with the via and contacts the interconnect, wherein a conductive trace includes the routing line, the interconnect and the pillar. Preferably, the opening extends through an insulative adhesive that attaches the routing line to the chip.

Abstract translation: 将导电迹线和绝缘基底连接到半导体芯片的方法包括提供半导体芯片，金属基底，绝缘基底，布线线和互连件，其中芯片包括导电垫，金属基底设置在 所述绝缘基板的远离所述芯片的一侧，所述布线线设置在所述绝缘基板的面向所述芯片的一侧，并且所述互连件延伸穿过所述绝缘基座中的通孔，并且电连接所述金属基座 形成一个延伸穿过绝缘基座并露出焊盘的开口，形成一个使导线与焊盘电连接的连接接头，并蚀刻金属基座，使金属基座的未蚀刻部分形成一个重叠的支柱 并且与通孔对齐并接触互连，其中导电迹线包括布线线，互连件和支柱。 优选地，开口延伸穿过将路由线连接到芯片的绝缘粘合剂。

公开(公告)号：US06949408B1

公开(公告)日：2005-09-27

申请号：US10356372

申请日：2003-02-01

Applicant: Charles W. C. Lin ,  Cheng-Lien Chiang

Inventor： Charles W. C. Lin ,  Cheng-Lien Chiang

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L24/18 ,  H01L23/3128 ,  H01L23/4985 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/18 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05599

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip, a metal base, an insulative base and a conductive trace, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, the conductive trace includes a contact terminal that extends through the insulative base, and the pad is exposed through an opening that extends through the metal base and the insulative base and is spaced from the contact terminal, then forming a connection joint that contacts and electrically connects the conductive trace and the pad, and then removing a portion of the metal base that contacts the contact terminal. Preferably, the opening extends through an insulative adhesive that attaches the chip to the conductive trace.

Abstract translation: 制造半导体芯片组件的方法包括提供半导体芯片，金属基底，绝缘基底和导电迹线，其中芯片包括导电垫，金属基底设置在绝缘基底的远离 芯片，导电迹线包括延伸穿过绝缘基底的接触端子，并且焊盘通过延伸穿过金属基底和绝缘基底的开口暴露，并且与接触端子间隔开，然后形成接触的连接接头 并且电连接导电迹线和焊盘，然后去除与接触端子接触的金属基底的一部分。 优选地，开口延伸穿过将芯片附接到导电迹线的绝缘粘合剂。

公开(公告)号：US06872591B1

公开(公告)日：2005-03-29

申请号：US10646415

申请日：2003-08-22

Applicant: Chia-Chung Wang ,  Charles W. C. Lin

Inventor： Chia-Chung Wang ,  Charles W. C. Lin

IPC: H01L21/48 ,  H01L23/31 ,  H05K3/40 ,  H01L21/44 ,  H01L21/50

CPC classification number: H01L23/3114 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/3512 ,  H05K3/4046 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/48 ,  H01L2224/18 ,  H01L2924/00012

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip, a conductive trace and a substrate, wherein the chip includes first and second opposing major surfaces and a conductive pad, the pad extends to the first surface of the chip, the substrate includes first and second opposing major surfaces, a conductive terminal and a dielectric base, the conductive terminal extends through the dielectric base to the first and second surfaces of the substrate, a cavity extends from the first surface of the substrate into the substrate, the first surfaces of the chip and the substrate face in a first direction, the second surfaces of the chip and the substrate face in a second direction, and the chip extends into the cavity, and then electrically connecting the conductive terminal to the pad using the conductive trace.

Abstract translation: 制造半导体芯片组件的方法包括提供半导体芯片，导电迹线和基板，其中所述芯片包括第一和第二相对的主表面和导电焊盘，所述焊盘延伸到所述芯片的第一表面，所述基板包括 第一和第二相对的主表面，导电端子和电介质基底，导电端子延伸穿过电介质基底到基板的第一和第二表面，空腔从基板的第一表面延伸到基板中，第一表面 的芯片和基板面朝向第一方向，芯片和基板的第二表面朝向第二方向，并且芯片延伸到空腔中，然后使用导电迹线将导电端子电连接到焊盘。

公开(公告)号：US06765287B1

公开(公告)日：2004-07-20

申请号：US10307134

申请日：2002-11-29

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2302

CPC classification number: H01L25/0657 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, and the pillars are disposed outside the peripheries of the chips and aligned with one another. The conductive bond contacts and electrically connects the pillars.

Abstract translation: 三维堆叠半导体封装包括第一和第二半导体芯片组件和导电结合。 第一半导体芯片组件包括第一半导体芯片和具有第一布线线和第一支柱的第一导电迹线。 第二半导体芯片组件包括第二半导体芯片和具有第二布线线和第二支柱的第二导电迹线。 芯片彼此对准，并且支柱设置在芯片周边的外侧并彼此对准。 导电键接触并电连接支柱。

公开(公告)号：US06436734B1

公开(公告)日：2002-08-20

申请号：US09878521

申请日：2001-06-11

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2144

CPC classification number: H01L21/4857 ,  H01L23/49811 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/062 ,  H05K3/4007 ,  H01L2924/00

Abstract: A method of manufacturing a support circuit includes providing a conductive layer with top and bottom surfaces,,providing a top etch mask on the top surface that includes an opening that exposes a portion of the top surface, providing a bottom etch mask on the bottom surface that includes an opening that exposes a portion of the bottom surface, applying an etch to the exposed portion of the top surface through the opening in the top etch mask, thereby etching partially but not completely through the conductive layer and forming a recessed portion in the conductive layer below the top surface, forming an insulative base on the recessed portion without forming the insulative base on the top surface, and applying an etch to the exposed portion of the bottom surface through the opening in the bottom etch mask, thereby forming a routing line in the recessed portion that extends to and is covered by the insulative base.

Abstract translation: 一种制造支撑电路的方法包括提供具有顶表面和底表面的导电层，在顶表面上提供顶部蚀刻掩模，其包括露出顶表面的一部分的开口，在底表面上提供底蚀刻掩模 其包括露出底表面的一部分的开口，通过顶部蚀刻掩模中的开口对顶表面的暴露部分施加蚀刻，从而通过导电层部分蚀刻但不完全蚀刻，并在其中形成凹陷部分 导电层，在凹陷部分上形成绝缘基底，而不在顶表面上形成绝缘基底，并且通过底部蚀刻掩模中的开口对底表面的暴露部分施加蚀刻，从而形成布线 在凹进部分中延伸并被绝缘基底覆盖的线。

公开(公告)号：US09018667B2

公开(公告)日：2015-04-28

申请号：US12758040

申请日：2010-04-12

Applicant: Charles W. C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

Inventor： Charles W. C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/495 ,  H05K1/02 ,  H01L33/48 ,  H01L33/64 ,  H05K3/00 ,  H05K3/38

CPC classification number: H01L21/486 ,  H01L23/3677 ,  H01L23/49575 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/32188 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/19041 ,  H05K1/0204 ,  H05K3/0061 ,  H05K3/386 ,  H05K2201/09054 ,  H05K2201/10106 ,  H05K2201/10969 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and first and second adhesives. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The heat spreader includes a post and a base. The post extends upwardly from the base through an opening in the first adhesive, and the base extends laterally from the post. The first adhesive extends between the base and the conductive trace and the second adhesive extends between the post and the conductive trace. The conductive trace provides signal routing between a pad and a terminal.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线以及第一和第二粘合剂。 半导体器件电连接到导电迹线并热连接到散热器。 散热器包括一个柱子和一个底座。 柱从基部穿过第一粘合剂中的开口向上延伸，并且基部从柱横向延伸。 第一粘合剂在基部和导电迹线之间延伸，并且第二粘合剂在柱和导电迹线之间延伸。 导电迹线提供焊盘和端子之间的信号路由。

公开(公告)号：US08927339B2

公开(公告)日：2015-01-06

申请号：US13299472

申请日：2011-11-18

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L21/60 ,  H01L23/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/19 ,  H01L21/4878 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/181 ,  H01L2924/00

Abstract: A method of making a semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive and a build-up circuitry is disclosed. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry includes a dielectric layer and conductive traces on the semiconductor device and the flange. The conductive traces provide signal routing for the semiconductor device.

Abstract translation: 公开了制造包括半导体器件，散热器，粘合剂和积聚电路的半导体组件的方法。 散热器包括凸块，底座和凸缘。 凸块限定一个空腔。 半导体器件安装在空腔处的凸块上，电连接到积聚电路并热连接到凸块。 凸起从基部延伸到粘合剂中的开口中，基部从与腔相对的凸起垂直延伸，并且凸缘从腔入口处的凸起横向延伸。 积聚电路包括介电层和半导体器件上的导电迹线和凸缘。 导电迹线为半导体器件提供信号路由。

公开(公告)号：US08901435B2

公开(公告)日：2014-12-02

申请号：US13615819

申请日：2012-09-14

Applicant: Charles W. C. Lin ,  Chia Chung Wang

Inventor： Charles W. C. Lin ,  Chia Chung Wang

IPC: H01L23/498 ,  H05K1/11

CPC classification number: H01L21/58 ,  H01L23/485 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/12042 ,  H01L2924/15172 ,  H01L2924/171 ,  Y10T428/24917 ,  H01L2924/014 ,  H01L2924/00

Abstract: A hybrid wiring board includes an interposer, a stopper, a stiffener and a build-up circuitry. The stopper is laterally aligned with and laterally extends beyond peripheral edges of the interposer in lateral directions. The interposer extends into an aperture of the stiffener and is electrically connected to the build-up circuitry. The build-up circuitry covers the stopper, the interposer and the stiffener and provides signal routing for the interposer. The stiffener provides mechanical support, ground/power plane and heat sink for the build-up circuitry.

Abstract translation: 混合布线板包括插入件，止动件，加强件和积聚电路。 止动件在横向方向上横向对齐并且横向延伸超过插入件的周边边缘。 插入器延伸到加强件的孔中并且电连接到积聚电路。 积聚电路覆盖止动器，插入器和加强件，并为插入器提供信号路由。 加强筋为建立电路提供机械支撑，接地/电源平面和散热器。