公开(公告)号：US06984576B1

公开(公告)日：2006-01-10

申请号：US10356800

申请日：2003-02-01

申请人： Charles W. C. Lin ,  Cheng-Lien Chiang

发明人： Charles W. C. Lin ,  Cheng-Lien Chiang

IPC分类号： H01L21/44

CPC分类号： H01L23/5389 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/11474 ,  H01L2224/12 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H05K3/4046 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/00012

摘要： A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a metal base, an insulative base, a routing line and an interconnect, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, the routing line is disposed on a side of the insulative base that faces towards the chip, and the interconnect extends through a via in the insulative base and electrically connects the metal base and the routing line, forming an opening that extends through the insulative base and exposes the pad, forming a connection joint that electrically connects the routing line and the pad, and etching the metal base such that an unetched portion of the metal base forms a pillar that overlaps and is aligned with the via and contacts the interconnect, wherein a conductive trace includes the routing line, the interconnect and the pillar. Preferably, the opening extends through an insulative adhesive that attaches the routing line to the chip.

摘要翻译： 将导电迹线和绝缘基底连接到半导体芯片的方法包括提供半导体芯片，金属基底，绝缘基底，布线线和互连件，其中芯片包括导电垫，金属基底设置在 所述绝缘基板的远离所述芯片的一侧，所述布线线设置在所述绝缘基板的面向所述芯片的一侧，并且所述互连件延伸穿过所述绝缘基座中的通孔，并且电连接所述金属基座 形成一个延伸穿过绝缘基座并露出焊盘的开口，形成一个使导线与焊盘电连接的连接接头，并蚀刻金属基座，使金属基座的未蚀刻部分形成一个重叠的支柱 并且与通孔对齐并接触互连，其中导电迹线包括布线线，互连件和支柱。 优选地，开口延伸穿过将路由线连接到芯片的绝缘粘合剂。

公开(公告)号：US20070228110A1

公开(公告)日：2007-10-04

申请号：US11758479

申请日：2007-06-05

申请人： Benjamin Eldridge ,  Gary Grube ,  Igor Khandros ,  Gaetan Mathieu

发明人： Benjamin Eldridge ,  Gary Grube ,  Igor Khandros ,  Gaetan Mathieu

IPC分类号： B23K20/00

CPC分类号： H01L24/72 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D21/02 ,  G01R1/0483 ,  G01R1/06711 ,  G01R1/07314 ,  G01R1/07342 ,  G01R1/07357 ,  G01R1/07378 ,  G01R31/2884 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/6715 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/67288 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/12 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/49 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/73251 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/78301 ,  H01L2224/81801 ,  H01L2224/81901 ,  H01L2224/85 ,  H01L2224/85043 ,  H01L2224/85045 ,  H01L2224/851 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20751 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4015 ,  H05K3/4092 ,  H05K7/1069 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49149 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/2075 ,  H01L2924/01204 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/01048 ,  H01L2224/72 ,  H01L2924/00012

摘要： Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics. A variety of techniques for configuring, severing, and overcoating the wire stem are disclosed. In an exemplary embodiment, a free end of a wire stem is bonded to a contact area on a substrate, the wire stem is configured to have a springable shape, the wire stem is severed to be free-standing by an electrical discharge, and the free-standing wire stem is overcoated by plating. A variety of materials for the wire stem (which serves as a falsework) and for the overcoat (which serves as a superstructure over the falsework) are disclosed. Various techniques are described for mounting the contact structures to a variety of electronic components (e.g., semiconductor wafers and dies, semiconductor packages, interposers, interconnect substrates, etc.), and various process sequences are described. The resilient contact structures described herein are ideal for making a “temporary” (probe) connections to an electronic component such as a semiconductor die, for burn-in and functional testing. The self-same resilient contact structures can be used for subsequent permanent mounting of the electronic component, such as by soldering to a printed circuit board (PCB). An irregular topography can be created on or imparted to the tip of the contact structure to enhance its ability to interconnect resiliently with another electronic component. Among the numerous advantages of the present invention is the great facility with which the tips of a plurality of contact structures can be made to be coplanar with one another. Other techniques and embodiments, such as wherein the falsework wirestem protrudes beyond an end of the superstructure, or is melted down, and wherein multiple free-standing resilient contact structures can be fabricated from loops, are described.

公开(公告)号：US06551861B1

公开(公告)日：2003-04-22

申请号：US09643445

申请日：2000-08-22

申请人： Charles W. C. Lin

发明人： Charles W. C. Lin

IPC分类号： H01L2144

CPC分类号： H01L23/3114 ,  H01L21/2885 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/12 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing a semiconductor chip assembly includes providing a semiconductor chip that includes a conductive pad, and providing a support circuit that includes an insulative base, a conductive trace and a through-hole that extends through the conductive trace and is covered by the base. One embodiment includes disposing an adhesive beneath the through-hole, mechanically attaching the chip to the support circuit using the adhesive such that a portion of the pad is directly beneath the through-hole, and then applying an etch to form openings in the base and the adhesive such that the openings and the through-hole expose the pad. Another embodiment includes disposing an adhesive beneath the through-hole, applying an etch to form openings in the base and the adhesive, and then mechanically attaching the chip to the support circuit using the adhesive such that the openings and the through-hole expose the pad. Preferably, a connection joint is formed inside the through-hole that extends through the opening in the adhesive and electrically connects the conductive trace and the pad.

摘要翻译： 制造半导体芯片组件的方法包括提供包括导电焊盘的半导体芯片，并且提供支撑电路，该支撑电路包括绝缘基底，导电迹线和延伸穿过导电迹线并被基底覆盖的通孔 。 一个实施例包括在通孔下方设置粘合剂，使用粘合剂将芯片机械地附接到支撑电路，使得垫的一部分直接在通孔下方，然后施加蚀刻以在基部中形成开口，并且 粘合剂使得开口和通孔露出垫。 另一实施例包括在通孔下方设置粘合剂，施加蚀刻以在基底和粘合剂中形成开口，然后使用粘合剂将芯片机械地附接到支撑电路，使得开口和通孔暴露衬垫 。 优选地，连接接头形成在通孔内部，该通孔延伸穿过粘合剂中的开口并电连接导电迹线和焊盘。

公开(公告)号：US06800506B1

公开(公告)日：2004-10-05

申请号：US10156469

申请日：2002-05-28

申请人： Charles W. C. Lin ,  Cheng-Lien Chiang

发明人： Charles W. C. Lin ,  Cheng-Lien Chiang

IPC分类号： H01L2144

CPC分类号： H01L23/5389 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/11474 ,  H01L2224/12 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H05K3/4046 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/00012

摘要： A method of making a semiconductor chip assembly includes providing a semiconductor chip and a laminated structure, wherein the chip includes a conductive pad, the laminated structure includes a conductive trace, an insulative base and a metal base, the conductive trace includes a routing line and a bumped terminal, the metal base and the routing line are disposed on opposite sides of the insulative base, and the bumped terminal includes a cavity that extends through the insulative base and into the metal base, removing a portion of the metal base that contacts the bumped terminal, and forming a connection joint that contacts and electrically connects the conductive trace and the pad.

摘要翻译： 制造半导体芯片组件的方法包括提供半导体芯片和层叠结构，其中所述芯片包括导电焊盘，所述层叠结构包括导电迹线，绝缘基底和金属基底，所述导电迹线包括布线线和 凸起端子，金属基座和布线线设置在绝缘基座的相对侧上，凸起端子包括延伸穿过绝缘基座并进入金属基座的空腔，去除与金属基座接触的部分 并且形成接触和电连接导电迹线和焊盘的连接接头。

公开(公告)号：US06786385B1

公开(公告)日：2004-09-07

申请号：US09533365

申请日：2000-03-22

申请人： Masayuki Kitajima ,  Masakazu Takesue ,  Yoshitaka Muraoka

发明人： Masayuki Kitajima ,  Masakazu Takesue ,  Yoshitaka Muraoka

IPC分类号： B23K108

CPC分类号： H01L24/742 ,  B23K1/0016 ,  B23K35/26 ,  B23K35/262 ,  B23K35/3013 ,  B23K2101/36 ,  H01L21/6835 ,  H01L24/81 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/11822 ,  H01L2224/1184 ,  H01L2224/11901 ,  H01L2224/12 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/1358 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/53178 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a semiconductor element having electrodes and metal bumps are attached to the electrodes. The metal bumps include copper cores and gold surface layers covering the cores. In addition, the metal bumps may include gold bump elements and solder bump elements connected together.

摘要翻译： 半导体器件包括具有电极的半导体元件和附接到电极的金属凸块。 金属凸块包括铜芯和覆盖芯的金表面层。 此外，金属凸块可以包括连接在一起的金突起元件和焊料凸块元件。

公开(公告)号：US06624648B2

公开(公告)日：2003-09-23

申请号：US10011335

申请日：2001-12-05

申请人： Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu

发明人： Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu

IPC分类号： G01R3102

CPC分类号： H05K3/4015 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/06711 ,  G01R1/06727 ,  G01R1/07378 ,  G01R31/2889 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/12 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/45 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/49 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4092 ,  H05K7/1069 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49222 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A probe card assembly includes a probe card, a space transformer, and an interposer disposed between the space transformer and the probe card. Suitable mechanisms for adjusting the orientation of the space transformer without changing the orientation of the probe card, and for determining what adjustments to make, are disclosed.

摘要翻译： 探针卡组件包括探针卡，空间变换器和设置在空间变压器和探针卡之间的插入器。 公开了用于调整空间变换器的取向而不改变探针卡的取向以及用于确定进行什么调整的适当机构。

公开(公告)号：US20180269075A1

公开(公告)日：2018-09-20

申请号：US15786676

申请日：2017-10-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： YINAN LI

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L21/563 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/12 ,  H01L2224/16225 ,  H01L2924/181 ,  H01L2924/00012

摘要： A semiconductor device package includes a substrate having a first surface and a second surface facing away from the first surface, a conductive column extending in the substrate between the first surface and the second surface, a dielectric layer on the first surface of the substrate, a redistribution structure provided in the dielectric layer and electrically connected to the conductive column, a semiconductor chip provided above the dielectric layer and electrically connected to the redistribution structure, and an encapsulation layer on the dielectric layer and encapsulating the semiconductor chip. The package is manufactured such that each of the substrate and the encapsulation layer is formed of molding compound.

公开(公告)号：US07759240B2

公开(公告)日：2010-07-20

申请号：US12024712

申请日：2008-02-01

申请人： Warren M. Farnworth ,  Salman Akram

发明人： Warren M. Farnworth ,  Salman Akram

IPC分类号： H01L21/44

CPC分类号： H05K3/321 ,  H01L21/288 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/12 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12044 ,  H01L2924/14 ,  H05K3/244 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2201/10984 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00012

摘要： An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also relates to assemblies comprising one or more of these substrates.

摘要翻译： 提供了一种用于在镀钯触点上形成具有钯金属层的衬底的方法，该衬底在衬底的至少一个接触点上并具有柔性导电聚合物凸块，优选两级环氧树脂。 本发明还涉及包括一个或多个这些基底的组件。

公开(公告)号：US20080119038A1

公开(公告)日：2008-05-22

申请号：US12024712

申请日：2008-02-01

申请人： Warren Farnworth ,  Salman Akram

发明人： Warren Farnworth ,  Salman Akram

IPC分类号： H01L21/44

CPC分类号： H05K3/321 ,  H01L21/288 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/12 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12044 ,  H01L2924/14 ,  H05K3/244 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2201/10984 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00012

摘要： An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also relates to assemblies comprising one or more of these substrates.

摘要翻译： 提供了一种用于在镀钯触点上形成具有钯金属层的衬底的方法，该衬底在衬底的至少一个接触点上并具有柔性导电聚合物凸块，优选两级环氧树脂。 本发明还涉及包括一个或多个这些基底的组件。

公开(公告)号：US20020067181A1

公开(公告)日：2002-06-06

申请号：US10011335

申请日：2001-12-05

申请人： FormFactor, Inc.

发明人： Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu

IPC分类号： G01R031/02 ,  H01R009/00 ,  H01R043/00

CPC分类号： H05K3/4015 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/06711 ,  G01R1/06727 ,  G01R1/07378 ,  G01R31/2889 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/12 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/45 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/49 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4092 ,  H05K7/1069 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49222 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A probe card assembly includes a probe card, a space transformer having resilient contact structures (probe elements) mounted directly to (i.e., without the need for additional connecting wires or the like) and extending from terminals on a surface thereof, and an interposer disposed between the space transformer and the probe card. The space transformer and interposer are nullstacked upnull so that the orientation of the space transformer, hence the orientation of the tips of the probe elements, can be adjusted without changing the orientation of the probe card. Suitable mechanisms for adjusting the orientation of the space transformer, and for determining what adjustments to make, are disclosed. The interposer has resilient contact structures extending from both the top and bottom surfaces thereof, and ensures that electrical connections are maintained between the space transformer and the probe card throughout the space transformer's range of adjustment, by virtue of the interposer's inherent compliance. Multiple die sites on a semiconductor wafer are readily probed using the disclosed techniques, and the probe elements can be arranged to optimize probing of an entire wafer. Composite interconnection elements having a relatively soft core overcoated by a relatively hard shell, as the resilient contact structures are described.