公开(公告)号：US11605609B2

公开(公告)日：2023-03-14

申请号：US16788428

申请日：2020-02-12

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/00 ,  H01L23/34 ,  H01L23/538 ,  H05K3/30 ,  H05K3/46 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L25/10 ,  H01L23/42 ,  H01L23/433 ,  H05K1/18 ,  H05K1/02 ,  H05K3/36

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

公开(公告)号：US10312194B2

公开(公告)日：2019-06-04

申请号：US15343259

申请日：2016-11-04

Applicant: General Electric Company

Inventor： Risto Ilkka Tuominen ,  Arun Virupaksha Gowda

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L25/16

Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a top surface of the insulating substrate, and a second electrical component coupled to a bottom surface of the insulating substrate. A first conductor layer is formed on the bottom surface of the insulating substrate and extends through a via formed therethrough to contact a contact pad of the first electrical component, with a portion of the first conductor layer positioned between the insulating substrate and the second electrical component. A second conductor layer is formed on the top surface of the insulating substrate and extends through another via formed therethrough to electrically couple with the first conductor layer and to contact a contact pad of the second electrical component.

公开(公告)号：US20190148279A1

公开(公告)日：2019-05-16

申请号：US16229049

申请日：2018-12-21

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Kaustubh Ravindra Nagarkar ,  Arun Virupaksha Gowda ,  James Wilson Rose

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.

公开(公告)号：US20180247924A1

公开(公告)日：2018-08-30

申请号：US15963559

申请日：2018-04-26

Applicant: General Electric Company

Inventor： Risto Ilkka Tuominen ,  Arun Virupaksha Gowda

IPC: H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48

Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.

公开(公告)号：US20180130747A1

公开(公告)日：2018-05-10

申请号：US15343259

申请日：2016-11-04

Applicant: General Electric Company

Inventor： Risto Ilkka Tuominen ,  Arun Virupaksha Gowda

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24146 ,  H01L2224/25171 ,  H01L2224/25174 ,  H01L2224/2518 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83851 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/13055 ,  H01L2924/143 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a top surface of the insulating substrate, and a second electrical component coupled to a bottom surface of the insulating substrate. A first conductor layer is formed on the bottom surface of the insulating substrate and extends through a via formed therethrough to contact a contact pad of the first electrical component, with a portion of the first conductor layer positioned between the insulating substrate and the second electrical component. A second conductor layer is formed on the top surface of the insulating substrate and extends through another via formed therethrough to electrically couple with the first conductor layer and to contact a contact pad of the second electrical component.

公开(公告)号：US09966361B1

公开(公告)日：2018-05-08

申请号：US15343248

申请日：2016-11-04

Applicant: General Electric Company

Inventor： Risto Ilkka Tuominen ,  Arun Virupaksha Gowda

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L23/485 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/485 ,  H01L2224/18 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012

Abstract: An electronics package includes an insulating substrate and electrical components coupled to a first surface of the insulating substrate. A multi-thickness conductor layer is formed on a second surface of the insulating substrate opposite the first surface. The multi-thickness conductor layer extends through vias in the insulating substrate to connect with contact pads of the electrical components. The multi-thickness conductor layer has a first thickness in a region proximate the first electrical component and a second thickness in a region proximate the second electrical component, the first thickness greater than the second thickness. The electronics package also includes a first redistribution layer having a conductor layer formed atop a portion of the multi-thickness conductor layer having the second thickness. A top surface of the conductor layer is co-planar with or substantially co-planar with a top surface of a portion of the multi-thickness conductor layer having the first thickness.

公开(公告)号：US20180082981A1

公开(公告)日：2018-03-22

申请号：US15269576

申请日：2016-09-19

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda

IPC: H01L25/065 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/5385 ,  H01L24/10 ,  H01L24/42 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/00012

Abstract: An integrated circuit (IC) device is described. The IC device includes a substrate. A connection component including a cavity therethrough is attached to the substrate. A memory die is positioned in the cavity of the connection component and is electrically coupled to the substrate. A logic die extends over the memory die and at least a portion of the connection component, and is electrically coupled to the connection component and the memory die. The connection component is formed free of through silicon vias and is electrically coupled to the substrate through wire bonding.

公开(公告)号：US09613932B2

公开(公告)日：2017-04-04

申请号：US14742773

申请日：2015-06-18

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00 ,  H05K3/30

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6836 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/27003 ,  H01L2224/27312 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/27416 ,  H01L2224/27418 ,  H01L2224/27422 ,  H01L2224/27436 ,  H01L2224/2781 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/3511 ,  H05K3/305 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/19 ,  H01L21/78 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.

公开(公告)号：US09391027B2

公开(公告)日：2016-07-12

申请号：US14844515

申请日：2015-09-03

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/00 ,  H05K1/18 ,  H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H05K3/46 ,  H05K1/02 ,  H05K3/30 ,  H01L23/42 ,  H01L23/433

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

公开(公告)号：US20160104666A1

公开(公告)日：2016-04-14

申请号：US14512562

申请日：2014-10-13

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/78 ,  H01L25/07 ,  H01L21/48

CPC classification number: H01L24/46 ,  H01L21/6835 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3164 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/03466 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/24137 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/4847 ,  H01L2224/48847 ,  H01L2224/4903 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/8203 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/1302 ,  H01L2924/13023 ,  H01L2924/13034 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.

Abstract translation: 功率覆盖（POL）结构包括具有设置在功率器件的上表面上的至少一个上接触焊盘的功率器件，以及具有耦合到功率器件的上表面的电介质层的POL互连层和金属化层 具有延伸穿过通过介电层形成的通孔并且电耦合到功率器件的至少一个上接触焊盘的金属互连。 POL结构还包括直接耦合到金属化层的至少一个铜引线键。