公开(公告)号：US07274088B2

公开(公告)日：2007-09-25

申请号：US10196305

申请日：2002-07-16

申请人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

发明人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

IPC分类号： H01L23/495 ,  H01L29/40

CPC分类号： H01L24/16 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

摘要： A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

摘要翻译： 提供一种具有引线框架作为芯片载体的翻转半导体封装，其中引线框架的多个引线至少形成有至少一个阻挡构件。 当通过焊料凸块将芯片安装在引线框架上时，每个焊料凸块在引线的阻挡件和引线的内端之间的位置附接到相应的一个引线。 在用于将焊料凸点润湿到引线的回流焊接过程中，阻挡构件将有助于控制焊料凸块的塌陷高度，从而增强焊料凸块对CTE产生的热应力的阻力（热膨胀系数）不匹配 在芯片和引线之间，从而防止芯片和引线之间的不完全的电连接。

公开(公告)号：US07199459B2

公开(公告)日：2007-04-03

申请号：US11126110

申请日：2005-05-09

申请人： Han-Ping Pu ,  Chien Ping Huang

发明人： Han-Ping Pu ,  Chien Ping Huang

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/28 ,  H01L23/31 ,  H01L23/52

CPC分类号： H01L23/3128 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/3862 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor package without bonding wires and a fabrication method are provided. The semiconductor package includes a substrate having a front surface and a back surface, two chips formed on the front surface, two dielectric layers formed on the chips respectively, two conductive trace layers formed on the dielectric layers respectively, an insulating layer formed on one of the dielectric layers, and a plurality of solder balls implanted on the back surface of the substrate. One of the dielectric layers is formed on one of the chips and attached to an entire non-active surface of the other of the chips.

摘要翻译： 提供了不具有接合线的半导体封装和制造方法。 半导体封装包括具有前表面和后表面的基板，形成在前表面上的两个芯片，分别形成在芯片上的两个电介质层，分别形成在电介质层上的两个导电迹线层，形成在绝缘层上的绝缘层 电介质层，以及注入到基板背面的多个焊球。 一个电介质层形成在一个芯片上并附着到另一个芯片的整个非有效表面。

公开(公告)号：US07057276B2

公开(公告)日：2006-06-06

申请号：US10690921

申请日：2003-10-21

申请人： Chang-Fu Lin ,  Han-Ping Pu ,  Chien-Ping Huang

发明人： Chang-Fu Lin ,  Han-Ping Pu ,  Chien-Ping Huang

IPC分类号： H01L23/10 ,  H01L23/34

CPC分类号： H01L23/367 ,  H01L23/3672 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16315 ,  H01L2224/05599

摘要： A semiconductor package with a heat sink is provided. At least one chip and a heat sink attached to the chip are mounted on a substrate. At least one slot is formed through at least one corner of the heat sink at a position attached to the substrate. An adhesive material is applied between the heat sink and substrate and over filled in the slot with an overflow of the adhesive material out of the slot. The adhesive material over filled in the slot provides an anchoring effect and increases its contact area with the heat sink to thereby firmly secure the heat sink on the substrate. Further, the slot formed at the corner of the heat sink can alleviate thermal stresses accumulated at the corner of the heat sink and thereby prevent delamination between the heat sink and the substrate.

摘要翻译： 提供了具有散热器的半导体封装。 连接到芯片的至少一个芯片和散热片安装在基板上。 在连接到基板的位置处，通过散热器的至少一个角部形成至少一个槽。 将粘合剂材料施加在散热器和衬底之间并且在填充在槽中并且粘合剂材料溢出出槽之外。 填充在槽中的粘合剂材料提供锚定效果并增加其与散热器的接触面积，从而将散热器牢固地固定在基板上。 此外，形成在散热器角落处的槽可以减轻积聚在散热器拐角处的热应力，从而防止散热器和基板之间的分层。

公开(公告)号：US06980438B2

公开(公告)日：2005-12-27

申请号：US10759863

申请日：2004-01-16

申请人： Chien-Ping Huang ,  Han-Ping Pu ,  Chin-Te Chen ,  Chang-Fu Lin

发明人： Chien-Ping Huang ,  Han-Ping Pu ,  Chin-Te Chen ,  Chang-Fu Lin

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/055 ,  H01L23/10 ,  H01L23/367 ,  H01L23/467 ,  H01L25/065 ,  H05K7/20

CPC分类号： H01L23/467 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/055 ,  H01L23/10 ,  H01L23/3672 ,  H01L23/3675 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00

摘要： A semiconductor package with a heat dissipating structure includes a substrate, a chip and a heat dissipating structure. The chip is mounted on and electrically connected to the substrate. The heat dissipating structure includes a first heat sink having at least one positioning portion, and at least one second heat sink having at least one second positioning portion and at least one hollow portion. The second heat sink is mounted on the substrate, and the first positioning portion of the first heat sink is attached to the second positioning portion of the second heat sink, allowing the chip to be accommodated in a space defined by the first heat sink, the hollow portion of the second heat sink and the substrate. This semiconductor package has good heat dissipating efficiency and is cost-effective to fabricate.

公开(公告)号：US06828665B2

公开(公告)日：2004-12-07

申请号：US10319262

申请日：2002-12-13

申请人： Han-Ping Pu ,  Chih-Ming Huang ,  Chien-Ping Huang

发明人： Han-Ping Pu ,  Chih-Ming Huang ,  Chien-Ping Huang

IPC分类号： H01L2302

CPC分类号： H01L23/5385 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/141 ,  H05K1/144 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/0401

摘要： A module device of stacked semiconductor packages and a method for fabricating the module device are proposed, wherein a first semiconductor package provided, and at least a second semiconductor package is stacked on and electrically connected to the first semiconductor package. The first semiconductor package includes a chip carrier for mounting at least a chip thereon; a circuit board positioned above and electrically connected to the chip carrier by a plurality of conductive elements; and an encapsulant for encapsulating the chip, conductive elements and encapsulant with a top surface of the circuit board being exposed, allowing the second semiconductor package to be electrically connected to the exposed top surface of the circuit board. As the circuit board is incorporated in the first semiconductor package by means of the encapsulant, it provides preferably reliability and workability for electrically connecting the second semiconductor package to the first semiconductor package.

公开(公告)号：US06498054B1

公开(公告)日：2002-12-24

申请号：US09585964

申请日：2000-06-02

申请人： Shih-Kuang Chiu ,  Ying-Chou Tsai ,  Han-Ping Pu

发明人： Shih-Kuang Chiu ,  Ying-Chou Tsai ,  Han-Ping Pu

IPC分类号： H01L2144

CPC分类号： H01L24/32 ,  H01L21/563 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/15151 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： A flip-chip underfill method is proposed for the purpose of underfilling a gap formed beneath a semiconductor chip mounted in a flip-chip manner over an underlying surface. The flip-chip underfill method comprises the following procedural steps of: preparing a dispensing needle having an outlet; then, moving the dispensing needle in such a manner as to position the outlet thereof at a corner point between the upper surface and the sidewall of the semiconductor chip; and finally injecting resin at the targeted corner point, which allows the injected resin from the outlet of the dispensing needle to flow down along the sidewall of the semiconductor chip to the edge of the lower surface of the semiconductor chip and subsequently fill into the gap through capillary action. This flip-chip underfill method is more advantageous to use than the prior art since it allows the dispensing needle to be unobstructed by any gold wires or passive components mounted beside the chip and also allows the injected resin to be substantially confined to the targeted area beneath the chip without being wasted.

摘要翻译： 提出了一种倒装底层填充方法，其目的在于在底层表面上以倒装芯片的方式填充形成在半导体芯片下面的间隙。 倒装底层填充方法包括以下步骤：准备具有出口的分配针; 然后，以将出口定位在半导体芯片的上表面和侧壁之间的角点处的方式移动分配针; 并且最终在目标角点注入树脂，这允许来自分配针的出口的注入的树脂沿着半导体芯片的侧壁向下流到半导体芯片的下表面的边缘，随后填充到间隙中 毛细作用。 这种倒装底层填充方法比现有技术更有利于使用，因为其允许分配针由安装在芯片旁边的任何金线或无源元件不受阻碍，并且还允许注入的树脂基本上限制在下面的目标区域 芯片不被浪费。

公开(公告)号：US06291264B1

公开(公告)日：2001-09-18

申请号：US09629072

申请日：2000-07-31

申请人： Wei-Sen Tang ,  Han-Ping Pu

发明人： Wei-Sen Tang ,  Han-Ping Pu

IPC分类号： H01L2144

CPC分类号： H01L24/32 ,  H01L21/563 ,  H01L24/28 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A flip-chip package technology is proposed for use to fabricate a dual-chip integrated circuit package that includes two semiconductor chips in a single package unit, which is characterized in the forming of a flash-barrier structure that can help prevent the underfill material used in flip-chip underfill process from flashing to other unintended areas. The flash-barrier structure can be either a protruded dam structure over the underlying semiconductor chip, or a groove in a coating layer formed over the underlying semiconductor chip. During flip-chip underfill process, the flash-barrier structure can confine the underfill material within the intended area and prevent the underfill material from flowing to other unintended areas such as nearby bonding pads, so that the finished package product can be assured in quality and reliability.

摘要翻译： 提出了一种倒装芯片封装技术，用于制造双芯片集成电路封装，其包括在单个封装单元中的两个半导体芯片，其特征在于形成闪光屏障结构，其可以帮助防止使用的底部填充材料 在从闪烁到其他非预期区域的倒装芯片底部填充过程中。 闪光屏障结构可以是下面的半导体芯片上的突出的坝结构，也可以是形成在下面的半导体芯片上的涂层中的凹槽。 在倒装芯片底部填充过程中，闪光屏障结构可以将底部填充材料限制在预期区域内，并防止底部填充材料流到其他非预期区域（例如附近的焊盘），从而可以确保成品包装产品的质量和 可靠性。

公开(公告)号：US06281578B1

公开(公告)日：2001-08-28

申请号：US09638989

申请日：2000-08-15

申请人： Randy H. Y. Lo ,  Chi-Chuan Wu ,  Han-Ping Pu ,  Eric Ko

发明人： Randy H. Y. Lo ,  Chi-Chuan Wu ,  Han-Ping Pu ,  Eric Ko

IPC分类号： H01L2334

CPC分类号： H01L23/49531 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A multi-chip module (MCM) integrated circuit package structure is proposed, which can be used to pack a plurality of semiconductor chips of different functions while nonetheless allowing the overall package size to be as small as some existing types of integrated circuit packages, such as the SO (Small Outline) and QFP (Quad Flat Package) types, so that it can be manufactured using the existing fabrication equipment. The proposed MCM integrated circuit package structure is characterized in the use of a substrate having a centrally-located opening, and at least one semiconductor chip is mounted on the front surface of the substrate and a semiconductor chip of a central-pad type having a plurality of centrally-located bonding pads is mounted on the back surface of the substrate with the centrally-located bonding pads being exposed through the opening. This arrangement allows the overall package size to be made very compact and also allows the wiring to the central-pad type semiconductor chip to be shortened.

摘要翻译： 提出了一种多芯片模块（MCM）集成电路封装结构，可用于封装多个不同功能的半导体芯片，同时允许整体封装尺寸与现有类型的集成电路封装一样小，如 作为SO（小外形）和QFP（四方扁平封装）类型，因此可以使用现有的制造设备制造。 所提出的MCM集成电路封装结构的特征在于使用具有居中定位的开口的衬底，并且至少一个半导体芯片安装在衬底的前表面上，以及具有多个中心焊盘的半导体芯片 中心定位的焊盘安装在基板的背面，中心位置的焊盘通过开口露出。 这种布置使得整体封装尺寸变得非常紧凑，并且还允许缩短到中心焊盘型半导体芯片的布线。

公开(公告)号：US09041223B2

公开(公告)日：2015-05-26

申请号：US13610050

申请日：2012-09-11

申请人： Yuh Chern Shieh ,  Han-Ping Pu ,  Yu-Feng Chen ,  Tin-Hao Kuo

发明人： Yuh Chern Shieh ,  Han-Ping Pu ,  Yu-Feng Chen ,  Tin-Hao Kuo

IPC分类号： H01L23/40 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/44 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1405 ,  H01L2224/14131 ,  H01L2224/145 ,  H01L2224/16104 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2224/05552

摘要： A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

摘要翻译： 描述了跟踪（BOT）结构。 BOT结构包括在第一工件的表面上具有金属迹线的第一工件，其中金属迹线具有第一轴线。 BOT结构还包括具有细长金属凸块的第二工件，其中细长金属凸块具有第二轴线，其中第二轴线与第一轴线成非零角度。 BOT结构还包括金属凸块，其中金属凸块电连接金属迹线和细长金属凸块。 还描述了具有BOT结构的封装和形成BOT结构的方法。

公开(公告)号：US08400178B2

公开(公告)日：2013-03-19

申请号：US12431927

申请日：2009-04-29

申请人： Han-Ping Pu ,  Mill-Jer Wang

发明人： Han-Ping Pu ,  Mill-Jer Wang

IPC分类号： G01R31/02

CPC分类号： H01L23/345 ,  G01R31/2856 ,  G01R31/2875 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a semiconductor device, the device includes a substrate, a front-end structure formed in the substrate, a back-end structure formed on the front-end structure, a heater embedded in the back-end structure and operable to generate heat, and a sensor embedded in the back-end structure and operable to sense a temperature of the semiconductor device.

摘要翻译： 本公开提供一种半导体器件，该器件包括衬底，形成在衬底中的前端结构，形成在前端结构上的后端结构，嵌入在后端结构中的加热器，可操作以产生 热和嵌入在后端结构中的传感器，并且可操作以感测半导体器件的温度。