公开(公告)号：US10199255B2

公开(公告)日：2019-02-05

申请号：US15446059

申请日：2017-03-01

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Alexander Binter ,  Bernhard Goller ,  Christian Grindling

IPC: H01L21/687 ,  H01L21/683 ,  B23C3/13 ,  B23Q3/08 ,  H01L21/67 ,  H01L21/304

Abstract: According to various embodiments, a workpiece planarization arrangement may include: a chuck including at least one portion configured to support one or more workpieces; and a planarization tool configured to planarize the at least one portion of the chuck and to planarize one or more workpieces on the at least one portion of the chuck; wherein the at least one portion of the chuck includes at least one of particles, pores and/or a polymer.

公开(公告)号：US20180374843A1

公开(公告)日：2018-12-27

申请号：US15631006

申请日：2017-06-23

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Iris Moder ,  Oliver Hellmund ,  Johannes Baumgartl ,  Annette Saenger ,  Barbara Eichinger ,  Doris Sommer ,  Jacob Tillmann Ludwig

IPC: H01L27/06 ,  H01L23/48 ,  H01L21/768

Abstract: An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.

公开(公告)号：US10049914B2

公开(公告)日：2018-08-14

申请号：US14946886

申请日：2015-11-20

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Hans-Joachim Schulze ,  Francisco Javier Santos Rodriguez ,  Iris Moder ,  Ingo Muri

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324

Abstract: According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried layer at least one of in or over the substrate by processing the first side of the substrate; thinning the substrate from the second side of the substrate, wherein the buried layer includes a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.

公开(公告)号：US20180144974A1

公开(公告)日：2018-05-24

申请号：US15858875

申请日：2017-12-29

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Johannes Baumgartl ,  Iris Moder ,  Ingo Muri ,  Thomas Christian Neidhart ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/76248 ,  H01L21/30608 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76272 ,  H01L21/76283 ,  H01L21/76898

Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.

公开(公告)号：US09954065B2

公开(公告)日：2018-04-24

申请号：US14936279

申请日：2015-11-09

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Frank Pfirsch ,  Hans-Joachim Schulze ,  Ingo Muri ,  Iris Moder ,  Johannes Baumgartl

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/324 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/1095 ,  H01L21/265 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3205 ,  H01L21/324 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66477 ,  H01L29/7397 ,  H01L29/78

Abstract: In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.

公开(公告)号：US20180040504A1

公开(公告)日：2018-02-08

申请号：US15229985

申请日：2016-08-05

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Ingo Muri ,  Johannes Baumgartl ,  Iris Moder ,  Thomas Christian Neidhart ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L21/306 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L21/76248 ,  H01L21/28 ,  H01L21/30608 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76272 ,  H01L21/76283 ,  H01L21/764 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.

公开(公告)号：US20170154808A1

公开(公告)日：2017-06-01

申请号：US14953362

申请日：2015-11-29

Applicant: Infineon Technologies AG

Inventor： Iris Moder ,  Ingo Muri ,  Johannes Baumgartl ,  Oliver Hellmund ,  Manfred Engelhardt ,  Hans-Joachim Schulze

IPC: H01L21/762

CPC classification number: H01L21/76267 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/31144 ,  H01L21/7621 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/76264 ,  H01L21/76272 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/76289 ,  H01L21/76297

Abstract: A method for fabricating a semiconductor device includes forming an opening in a first epitaxial lateral overgrowth region to expose a surface of the semiconductor substrate within the opening. The method further includes forming an insulation region at the exposed surface of the semiconductor substrate within the opening and filling the opening with a second semiconductor material to form a second epitaxial lateral overgrowth region using a lateral epitaxial growth process.

公开(公告)号：US20170148664A1

公开(公告)日：2017-05-25

申请号：US14946886

申请日：2015-11-20

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Hans-Joachim Schulze ,  Francisco Javier Santos Rodriguez ,  Iris Moder ,  Ingo Muri

IPC: H01L21/762 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L21/76243 ,  H01L21/02005 ,  H01L21/26533 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/7806

Abstract: According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried layer at least one of in or over the substrate by processing the first side of the substrate; thinning the substrate from the second side of the substrate, wherein the buried layer includes a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.

公开(公告)号：US20160225626A1

公开(公告)日：2016-08-04

申请号：US15049192

申请日：2016-02-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Hans-Joachim Schulze ,  Ingo Muri ,  Friedrich Kroener ,  Werner Schustereder

IPC: H01L21/265 ,  H01L21/3063 ,  H01L21/324

CPC classification number: H01L21/26513 ,  H01L21/263 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3063 ,  H01L21/3242

Abstract: A method for producing a semiconductor is disclosed, the method having: providing a semiconductor body having a first side and a second side; forming an n-doped zone in the semiconductor body by a first implantation into the semiconductor body via the first side to a first depth location of the semiconductor body; and forming a p-doped zone in the semiconductor body by a second implantation into the semiconductor body via the second side to a second depth location of the semiconductor body, a pn-junction forming between said n-doped zone and said p-doped zone in the semiconductor body.

公开(公告)号：US20160053397A1

公开(公告)日：2016-02-25

申请号：US14467106

申请日：2014-08-25

Applicant: Infineon Technologies AG

Inventor： Friedrich Kroener ,  Ingo Muri

IPC: C25D5/02 ,  C25D5/18 ,  C25D17/00 ,  C25D5/34

CPC classification number: C25D15/00 ,  C25D3/12 ,  C25D3/38 ,  C25D3/46 ,  C25D3/48 ,  C25D5/02 ,  C25D5/022 ,  C25D5/10 ,  C25D5/18 ,  C25D5/34 ,  C25D17/00 ,  C25D17/001 ,  C25D21/10

Abstract: A method of forming a composite material is provided. The method may include: arranging a suspension in physical contact with a carrier, wherein the suspension may comprise an electrolyte and a plurality of particles of a first component of the composite material; causing the particles of the first component of the composite material to sediment on the carrier, wherein a plurality of spaces may be formed between the sedimented particles; and forming by electroplating a second component of the composite material from the electrolyte in at least a fraction of the plurality of spaces.

Abstract translation: 提供了形成复合材料的方法。 该方法可以包括：将悬浮液布置成与载体物理接触，其中悬浮液可以包含电解质和复合材料的第一组分的多个颗粒; 导致复合材料的第一组分的颗粒沉积在载体上，其中可以在沉积的颗粒之间形成多个空间; 以及通过在所述多个空间的至少一部分中从所述电解质中电镀所述复合材料的第二组分而形成。