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公开(公告)号:US10593607B2
公开(公告)日:2020-03-17
申请号:US15145760
申请日:2016-05-03
Applicant: Micron Technology, Inc.
Inventor: Hong Wan Ng , Choon Kuan Lee , David J. Corisis , Chin Hui Chong
Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.
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公开(公告)号:US10522515B2
公开(公告)日:2019-12-31
申请号:US16285081
申请日:2019-02-25
Applicant: Micron Technology, Inc.
Inventor: Kevin Gibbons , Tracy V. Reynolds , David J. Corisis
Abstract: Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture.
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43.
公开(公告)号:US10448509B2
公开(公告)日:2019-10-15
申请号:US14797721
申请日:2015-07-13
Applicant: Micron Technology, Inc.
Inventor: David J. Corisis , Choon Kuan Lee , Chin Hui Chong
IPC: H05K1/11 , H05K1/16 , H05K3/10 , H05K3/42 , H05K3/46 , H01L21/02 , H01L21/44 , H01L21/48 , H01L23/48 , H01L23/52 , G01R31/02 , H05K1/02 , H01L21/768 , H01L23/498 , H01L23/66 , G06F1/16 , H05K1/18
Abstract: Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.
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公开(公告)号:US10312173B2
公开(公告)日:2019-06-04
申请号:US15936715
申请日:2018-03-27
Applicant: Micron Technology, Inc.
Inventor: Matt E. Schwab , J. Michael Brooks , David J. Corisis
IPC: H01L23/31 , H01L23/16 , H01L23/00 , H01L25/065 , H01L23/492 , H01L23/36
Abstract: Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.
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45.
公开(公告)号:US10008468B2
公开(公告)日:2018-06-26
申请号:US15388166
申请日:2016-12-22
Applicant: Micron Technology, Inc.
Inventor: Choon Kuan Lee , Chin Hui Chong , David J. Corisis
CPC classification number: H01L24/29 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/50 , H01L2224/06181 , H01L2224/16145 , H01L2224/29005 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06572 , H01L2924/00014 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.
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公开(公告)号:US09960094B2
公开(公告)日:2018-05-01
申请号:US15141682
申请日:2016-04-28
Applicant: Micron Technology, Inc.
Inventor: Matt E. Schwab , J. Michael Brooks , David J. Corisis
IPC: H01L23/31 , H01L23/16 , H01L25/065 , H01L23/492 , H01L23/36 , H01L23/00
CPC classification number: H01L23/3128 , H01L23/16 , H01L23/36 , H01L23/4924 , H01L24/06 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/06135 , H01L2224/06136 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/83192 , H01L2224/838 , H01L2225/0651 , H01L2225/06575 , H01L2225/06589 , H01L2225/06593 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/16235 , H01L2924/16788 , H01L2924/181 , H01L2924/351 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.
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公开(公告)号:US20170271228A1
公开(公告)日:2017-09-21
申请号:US15612174
申请日:2017-06-02
Applicant: Micron Technology, Inc.
Inventor: David J. Corisis , Choon Kuan Lee , Chin Hui Chong
CPC classification number: H01L23/3107 , H01L21/568 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L2224/05554 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2224/85001 , H01L2224/97 , H01L2924/00 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2224/85 , H01L2924/00012 , H01L2924/207
Abstract: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.
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48.
公开(公告)号:US09768121B2
公开(公告)日:2017-09-19
申请号:US15144699
申请日:2016-05-02
Applicant: Micron Technology, Inc.
Inventor: David J. Corisis , Chin Hui Chong , Choon Kuan Lee
IPC: H01L23/538 , H01L25/065 , H01L25/11 , H01L23/00 , H01L25/07 , H01L21/56 , H01L23/31 , H01L23/498 , H01L25/10 , H01L21/66 , H01L23/053
CPC classification number: H01L23/053 , H01L21/56 , H01L21/561 , H01L22/10 , H01L23/3128 , H01L23/3178 , H01L23/49805 , H01L23/49861 , H01L23/5389 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/45 , H01L24/46 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/074 , H01L25/105 , H01L25/117 , H01L2224/05554 , H01L2224/16 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/484 , H01L2224/48599 , H01L2224/4911 , H01L2224/4912 , H01L2224/49171 , H01L2224/73265 , H01L2224/81 , H01L2224/85 , H01L2224/97 , H01L2225/06503 , H01L2225/06506 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06548 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2225/1064 , H01L2225/1088 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/12042 , H01L2924/14 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/1627 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
Abstract: Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.
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49.
公开(公告)号:US09530748B2
公开(公告)日:2016-12-27
申请号:US14604545
申请日:2015-01-23
Applicant: Micron Technology, Inc.
Inventor: Choon Kuan Lee , Chin Hui Chong , David J. Corisis
IPC: H01L23/02 , H01L23/00 , H01L21/768 , H01L23/31 , H01L23/48 , H01L25/065 , H01L25/00
CPC classification number: H01L24/29 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/50 , H01L2224/06181 , H01L2224/16145 , H01L2224/29005 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06572 , H01L2924/00014 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.
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50.
公开(公告)号:US20160358831A1
公开(公告)日:2016-12-08
申请号:US15144699
申请日:2016-05-02
Applicant: Micron Technology, Inc.
Inventor: David J. Corisis , Chin Hui Chong , Choon Kuan Lee
IPC: H01L23/053 , H01L25/065 , H01L23/538 , H01L23/00 , H01L23/31 , H01L23/498
CPC classification number: H01L23/053 , H01L21/56 , H01L21/561 , H01L22/10 , H01L23/3128 , H01L23/3178 , H01L23/49805 , H01L23/49861 , H01L23/5389 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/45 , H01L24/46 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/074 , H01L25/105 , H01L25/117 , H01L2224/05554 , H01L2224/16 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/484 , H01L2224/48599 , H01L2224/4911 , H01L2224/4912 , H01L2224/49171 , H01L2224/73265 , H01L2224/81 , H01L2224/85 , H01L2224/97 , H01L2225/06503 , H01L2225/06506 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06548 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2225/1064 , H01L2225/1088 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/12042 , H01L2924/14 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/1627 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
Abstract: Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.
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