公开(公告)号：US20210043571A1

公开(公告)日：2021-02-11

申请号：US16887458

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.

公开(公告)号：US20200350221A1

公开(公告)日：2020-11-05

申请号：US16932948

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzuan-Horng Liu ,  Chen-Hua Yu ,  Hsien-Pin Hu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: H01L21/66 ,  H01L23/498 ,  G01R1/073 ,  H01L23/522 ,  H01L23/58 ,  H01L21/48

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

公开(公告)号：US10734295B2

公开(公告)日：2020-08-04

申请号：US16148169

申请日：2018-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzuan-Horng Liu ,  Chen-Hua Yu ,  Hsien-Pin Hu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: H01L21/48 ,  H01L21/66 ,  H01L23/498 ,  G01R1/073 ,  H01L23/522 ,  H01L23/58 ,  H01L21/56 ,  H01L21/683

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

公开(公告)号：US20190128958A1

公开(公告)日：2019-05-02

申请号：US16232373

申请日：2018-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC: G01R31/28 ,  H01L21/66 ,  G01R1/04 ,  G01R31/26 ,  H01L23/00

CPC classification number: G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

公开(公告)号：US09818720B2

公开(公告)日：2017-11-14

申请号：US14981458

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hsin Wei ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Wei-Ming Chen

IPC: H01L23/34 ,  H01L23/52 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H05K3/36 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H05K3/363

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first chip structure and a second chip structure. Heights of the first chip structure and the second chip structure are different. The chip package also includes a package layer covering sidewalls of the first chip structure and sidewalls of the second chip structure. Top surfaces of the first chip structure and the second chip structure are not covered by the package layer.

公开(公告)号：US20250149486A1

公开(公告)日：2025-05-08

申请号：US18433908

申请日：2024-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Jen Chang ,  Chung-Yu Lu ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Hsien-Pin Hu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes forming a first conductive pillar on an interposer; forming a second conductive pillar on the interposer, wherein the second conductive pillar includes a barrier layer; bonding a first semiconductor device to the first conductive pillar by a first bonding region that includes more inter-metallic compound than solder; and bonding the first semiconductor device to the second conductive pillar by a second bonding region that includes more solder than inter-metallic compound.

公开(公告)号：US20250054879A1

公开(公告)日：2025-02-13

申请号：US18931965

申请日：2024-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen Hsin Wei ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Weiming Chris Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532 ,  H01L23/58 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.

公开(公告)号：US20240387385A1

公开(公告)日：2024-11-21

申请号：US18785053

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.

公开(公告)号：US20240297166A1

公开(公告)日：2024-09-05

申请号：US18664483

申请日：2024-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/4803 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US11967546B2

公开(公告)日：2024-04-23

申请号：US17870099

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L23/5385 ,  H01L2224/023 ,  H01L2225/107

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.