公开(公告)号：US09502343B1

公开(公告)日：2016-11-22

申请号：US14858558

申请日：2015-09-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Hsien-Wei Chen ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Li-Han Hsu ,  Wei-Cheng Wu

IPC分类号： H01L23/52 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L23/49838 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/585 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/94 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10336 ,  H01L2924/10337 ,  H01L2924/10338 ,  H01L2924/10339 ,  H01L2924/10342 ,  H01L2924/10351 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11

摘要： A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.

摘要翻译： 一种结构包括金属焊盘，具有覆盖金属焊盘的边缘部分的部分的钝化层以及钝化层上的虚设金属板。 虚拟金属板在其中具有多个通孔。 虚拟金属板具有锯齿形边。 电介质层具有覆盖在虚拟金属板上的第一部分，填充第一多个通孔的第二部分和与第一锯齿状边缘接触的第三部分。

公开(公告)号：US20160240391A1

公开(公告)日：2016-08-18

申请号：US14688437

申请日：2015-04-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Lai Wei Chih

IPC分类号： H01L21/56 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/768

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/1511 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/83005

摘要： Package structures and methods of forming package structures are described. A method includes depositing and patterning a first dielectric material. The first dielectric material is deposited in first and second package component regions and in a scribe line region. The scribe line region is disposed between the first and second package component regions. The patterning the first dielectric material forms a first dielectric layer in each of the first and second package component regions and a dummy block in the scribe line region. The dummy block is separated from the first dielectric layer in each of the first and second package component regions. The method further includes forming a metallization pattern on the first dielectric layer; depositing a second dielectric material on the first dielectric layer and the metallization pattern; and patterning the second dielectric material to form a second dielectric layer.

摘要翻译： 描述形成封装结构的封装结构和方法。 一种方法包括沉积和图案化第一介电材料。 第一介电材料沉积在第一和第二封装部件区域和划线区域中。 划线区域设置在第一和第二包装部件区域之间。 图案化第一介电材料在第一和第二封装分量区域中的每一个中形成第一介电层，在划线区域中形成虚拟块。 该虚拟块与第一和第二封装分量区域中的每一个中的第一介电层分离。 该方法还包括在第一介电层上形成金属化图案; 在第一介电层和金属化图案上沉积第二电介质材料; 以及图案化所述第二电介质材料以形成第二电介质层。

公开(公告)号：US09299649B2

公开(公告)日：2016-03-29

申请号：US13763335

申请日：2013-02-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Wei Chiu ,  Cheng-Hsien Hsieh ,  Hsien-Pin Hu ,  Kuo-Ching Hsu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L23/12 ,  H01L23/053 ,  H01L23/498 ,  H01L21/683 ,  H01L21/56

CPC分类号： H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/13 ,  H01L2224/73204

摘要： Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

摘要翻译： 本公开的实施例包括半导体器件和形成半导体器件的方法。 一个实施例是一种半导体器件，包括由多个薄膜层和设置在其中的多个金属层组成的互连结构，多个金属层中的每一个具有基本上相同的顶表面积，以及模具，其包括活性表面和 与所述有源表面相对的背面，所述有源表面直接耦合到所述互连结构的第一侧。 半导体器件还包括直接耦合到互连结构的第二侧的第一连接器，第二侧与第一侧相对。

公开(公告)号：US20230154863A1

公开(公告)日：2023-05-18

申请号：US18155672

申请日：2023-01-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Cheng Wu ,  Chien-Chia Chiu ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Meng-Tsan Lee ,  Tsung-Shu Lin

IPC分类号： H01L23/552 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/488 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L23/552 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/31 ,  H01L23/488 ,  H01L23/5384 ,  H01L24/14

摘要： A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

公开(公告)号：US20230054020A1

公开(公告)日：2023-02-23

申请号：US17981465

申请日：2022-11-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Chih Lai ,  Chien-Chia Chiu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Yu-Chen Hsu

IPC分类号： H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L21/52 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498

摘要： A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

公开(公告)号：US20220093526A1

公开(公告)日：2022-03-24

申请号：US17542527

申请日：2021-12-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Cheng Wu ,  Chien-Chia Chiu ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Meng-Tsan Lee ,  Tsung-Shu Lin

IPC分类号： H01L23/552 ,  H01L23/00 ,  H01L23/488 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538

摘要： A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

公开(公告)号：US10950577B2

公开(公告)日：2021-03-16

申请号：US16661636

申请日：2019-10-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

摘要： An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.

公开(公告)号：US10833030B2

公开(公告)日：2020-11-10

申请号：US16390814

申请日：2019-04-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Hsien-Wei Chen ,  Chen-Hua Yu ,  Tsung-Shu Lin ,  Wei-Cheng Wu

IPC分类号： H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L23/48 ,  H01L23/31

摘要： A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.

公开(公告)号：US10700045B2

公开(公告)日：2020-06-30

申请号：US16675696

申请日：2019-11-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Hsien-Wei Chen ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Wei-Cheng Wu

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

摘要： Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively. The first opening, the second opening, the third opening, and the fourth opening are physically separated from each other.

公开(公告)号：US10665474B2

公开(公告)日：2020-05-26

申请号：US16362012

申请日：2019-03-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Wei Chiu ,  Cheng-Hsien Hsieh ,  Hsien-Pin Hu ,  Kuo-Ching Hsu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L21/683 ,  H01L21/56

摘要： Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.