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    3D semiconductor device(s) and structure(s) with electronic control units
    51.
    发明授权
    3D semiconductor device(s) and structure(s) with electronic control units 有权

    公开(公告)号：US11270988B2

    公开(公告)日：2022-03-08

    申请号：US17151867

    申请日：2021-01-19

    Applicant: Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/473 ,  H01L21/768 ,  H01L25/00 ,  H01L25/065

    Abstract: A 3D device, the first level including first transistors and a first interconnect; a second level with second transistors overlaying the first level; a third level with third transistors overlaying the second level; a plurality of electronic circuit units (ECUs), where each ECU includes a first circuit with a portion of the first transistors, where each of the ECUs includes a second circuit including a portion of the second transistors, where each of the plurality of ECUs includes a third circuit, which includes a portion of the third transistors, where each of the ECUs includes a vertical data bus, where the vertical data bus has between eight pillars and three hundreds pillars, where the vertical data bus provides electrical connections between the first and second circuits, where the third level includes an array of memory cells, and where the second circuit includes a memory control circuit.

    Semiconductor device and structure
    54.
    发明授权
    Semiconductor device and structure 有权
    半导体器件及结构

    公开(公告)号：US09000557B2

    公开(公告)日：2015-04-07

    申请号：US13423200

    申请日：2012-03-17

    Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

    Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

    IPC: H01L23/532 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L21/8238

    CPC classification number: H01L21/8221 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L2224/16225 ,  H01L2224/73253

    Abstract: A device including a first layer of first transistors interconnected by at least one first interconnection layer, where the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, where the second layer is less than about 2 micron thick, where the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, where the connection path includes at least one through-layer via, where the at least one through-layer via is formed through and in direct contact with a source or drain of at least one of the second transistors.

    Abstract translation: 一种器件，包括由至少一个第一互连层互连的第一层第一晶体管，其中第一互连层包括铜或铝，第二层包括第二晶体管，第二层覆盖第一互连层，其中第二层较少 大于约2微米厚，其中第二层具有热膨胀系数; 以及将所述第二晶体管中的至少一个连接到所述第一互连层的连接路径，其中所述连接路径包括至少一个贯通层通孔，其中所述至少一个贯通层通孔形成为通过并直接与源极接触 或漏极的至少一个第二晶体管。

    Semiconductor device and structure for heat removal
    55.
    发明授权
    Semiconductor device and structure for heat removal 有权
    半导体器件和结构的散热

    公开(公告)号：US08975670B2

    公开(公告)日：2015-03-10

    申请号：US13555152

    申请日：2012-07-22

    Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

    Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

    IPC: H01L29/80 ,  H01L23/552 ,  H01L23/48 ,  H01L27/06

    CPC classification number: H01L23/552 ,  H01L23/481 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.

    Abstract translation: 一种半导体器件，包括：具有包括第一晶体管的第一层的半导体衬底; 覆盖第一层的屏蔽层; 覆盖所述屏蔽层的第二层，所述第二层包括第二晶体管; 其中所述屏蔽层是具有用于所述第一晶体管和所述第二晶体管之间的连接的多个区域的大部分连续的层，并且其中所述第二晶体管包括单晶区域。

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