公开(公告)号：US20130328167A1

公开(公告)日：2013-12-12

申请号：US13489940

申请日：2012-06-06

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Baozhen Li ,  Keith Kwong Hon Wong

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Baozhen Li ,  Keith Kwong Hon Wong

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/75 ,  H01L23/5223 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-insulator-metal (MIM) capacitor structure integrated within a back-end-of-the-line (BEOL) structure is provided. The MIM capacitor structure includes a lower electrode, i.e., a first conductive material, embedded within a dielectric material of the BEOL structure, a dielectric material liner having a dielectric constant of equal to, or greater than, silicon dioxide located atop the lower electrode, and an upper electrode, i.e., a second conductive material, positioned between vertical portions of the dielectric material liner and atop a horizontal connecting portion of the dielectric material liner. In accordance with the present disclosure, the vertical portions of the dielectric material liner do not extend onto an upper surface of the dielectric material that includes the lower electrode.

摘要翻译： 提供集成在后端（BEOL）结构中的金属 - 绝缘体 - 金属（MIM）电容器结构。 MIM电容器结构包括嵌入在BEOL结构的电介质材料中的下电极，即第一导电材料，具有等于或大于位于下电极顶部的二氧化硅的介电常数的介电材料衬垫， 以及位于电介质材料衬垫的垂直部分之间并且位于介电材料衬里的水平连接部分顶部的上电极，即第二导电材料。 根据本公开，电介质材料衬垫的垂直部分不延伸到包括下电极的电介质材料的上表面上。

公开(公告)号：US08563419B2

公开(公告)日：2013-10-22

申请号：US13418659

申请日：2012-03-13

申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Daniel C. Edelstein

发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Daniel C. Edelstein

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing the IC is provided, and more particularly, a method of fabricating a cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage. The method includes forming an interconnect in an insulation material, and selectively depositing a metal cap material on the interconnect. The metal cap material includes RuX, where X is at least one of Boron and Phosphorous.

摘要翻译： 提供了一种制造IC的方法，更具体地说，涉及一种基本上消除电迁移（EM）损伤的制造用于后端（BEOL）互连的帽的方法。 该方法包括在绝缘材料中形成互连，并且在互连上选择性地沉积金属帽材料。 金属帽材料包括RuX，其中X是硼和磷中的至少一种。

公开(公告)号：US08470706B2

公开(公告)日：2013-06-25

申请号：US13602119

申请日：2012-09-01

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US08420531B2

公开(公告)日：2013-04-16

申请号：US13164929

申请日：2011-06-21

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Steven E. Molis

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Steven E. Molis

IPC分类号： H01L21/4763

CPC分类号： H01L23/52 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76867 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, the method includes forming at least one opening into an interconnect dielectric material. A nitrogen enriched dielectric surface layer is formed within exposed surfaces of the interconnect dielectric material utilizing thermal nitridation. A metal diffusion barrier liner is formed on the nitrogen enriched dielectric surface. During and/or after the formation of the metal diffusion barrier liner, a metal nitride liner forms in-situ in a lower region of the metal diffusion barrier liner. A conductive material is then formed on the metal diffusion barrier liner. The conductive material, the metal diffusion barrier liner and the metal nitride liner that are located outside of the at least one opening are removed to provide a planarized conductive material, a planarized metal diffusion barrier liner and a planarized metal nitride liner, each of which includes an upper surface that is co-planar with the nitrogen enriched dielectric surface layer of the interconnect dielectric material.

摘要翻译： 制造互连结构的替代方法，其中提供了包括在互连电介质材料和上覆金属扩散阻挡衬里之间形成的原位形成的金属氮化物衬垫的增强扩散屏障。 在一个实施例中，该方法包括在互连电介质材料中形成至少一个开口。 利用热氮化在互连电介质的暴露表面内形成富氮介电表面层。 在富氮电介质表面上形成金属扩散阻挡衬垫。 在形成金属扩散阻挡衬里期间和/或之后，金属氮化物衬垫在金属扩散阻挡衬里的下部区域中原位形成。 然后在金属扩散阻挡衬里上形成导电材料。 移除位于至少一个开口外侧的导电材料，金属扩散阻挡衬垫和金属氮化物衬垫，以提供平坦化的导电材料，平坦化的金属扩散阻挡衬垫和平坦化的金属氮化物衬垫，每个衬垫包括 与互连电介质材料的富氮介电表面层共平面的上表面。

公开(公告)号：US08336204B2

公开(公告)日：2012-12-25

申请号：US12509885

申请日：2009-07-27

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami

IPC分类号： H01K3/10

CPC分类号： H01L21/76846 ,  H01L21/76844 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.

摘要翻译： 提供了包括直接位于扩散阻挡层和Cu合金种子层之间的合金衬垫的互连结构以及用于形成这种互连结构的方法。 本发明的合金衬垫通过使预先沉积的扩散阻挡金属合金层与覆盖的Cu合金种子层热反应形成。 在热反应期间，来自扩散阻挡层和Cu合金种子层的金属合金在扩散阻挡层和Cu籽晶层之间反应形成金属合金反应产物。

公开(公告)号：US20120306018A1

公开(公告)日：2012-12-06

申请号：US13149797

申请日：2011-05-31

申请人： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

发明人： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

IPC分类号： H01L29/772 ,  H01L29/92 ,  H01L21/20 ,  H01L29/02

CPC分类号： H01L23/481 ,  H01L21/02667 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/53238 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L27/016 ,  H01L27/0688 ,  H01L29/66984 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

摘要： A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.

摘要翻译： 单片集成电路和方法包括基板，单片集成在基板上的多个半导体器件层以及具有互连多个半导体器件层的通孔的金属布线层。 半导体器件层没有与衬底接合或结合界面。 使用单个衬底制造单片集成电路的方法包括在衬底上制造半导体器件，在半导体器件上制造至少一个金属布线层，形成与至少一个金属布线层一体接触的至少一个电介质层 形成通过所述至少一个电介质层的接触开口以暴露所述至少一个金属布线层的区域，从所述基板一体地形成所述电介质层上的第二半导体层，并与所述至少一个金属布线层 通过所述接触开口，以及在所述第二半导体层中形成多个非线性半导体器件。

公开(公告)号：US08294270B2

公开(公告)日：2012-10-23

申请号：US13116622

申请日：2011-05-26

申请人： Daniel C. Edelstein ,  Edward C. Cooney, III ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Edward C. Cooney, III ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Anthony K. Stamper

IPC分类号： H01L23/52

CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/12493 ,  H01L2924/00

摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

摘要翻译： 通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性 通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。 通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。

公开(公告)号：US08293634B2

公开(公告)日：2012-10-23

申请号：US12187646

申请日：2008-08-07

申请人： Felix P. Anderson ,  William Cote ,  Daniel C. Edelstein ,  Thomas L. McDevitt ,  Anthony K. Stamper

发明人： Felix P. Anderson ,  William Cote ,  Daniel C. Edelstein ,  Thomas L. McDevitt ,  Anthony K. Stamper

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2221/1036 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01006

摘要： Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

摘要翻译： 具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。 该结构包括在至少一部分没有氟边界层的电介质层中形成的沟槽。 该结构还包括在沟槽中的铜线，其至少其底部与沟槽的非氟化物边界层接触。 无铅焊料凸块与铜线电接触。

公开(公告)号：US20120228771A1

公开(公告)日：2012-09-13

申请号：US13044660

申请日：2011-03-10

申请人： Daniel C. Edelstein ,  Takeshi Nogami

发明人： Daniel C. Edelstein ,  Takeshi Nogami

IPC分类号： H01L23/48 ,  C23C16/44 ,  C23C16/52 ,  C23C16/458 ,  C23C16/46 ,  H01L21/768 ,  C23C16/455

CPC分类号： C23C16/45523 ,  C23C16/14 ,  C23C16/18 ,  C23C16/44 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method for forming a multi-layered seed layer for semiconductor interconnections are disclosed. Specifically, the method and structure involves utilizing sequential catalytic chemical vapor deposition, which is followed by annealing, to form the multi-layered seed layer of an interconnect structure. The multi-layered seed layer will improve electromigration resistance, decrease void formation, and enhance reliability of ultra-large-scale integration (ULSI) chips.

摘要翻译： 公开了用于形成用于半导体互连的多层种子层的互连结构和方法。 具体地说，该方法和结构涉及利用顺序的催化化学气相沉积，随后进行退火以形成互连结构的多层种子层。 多层种子层将提高超大规模集成（ULSI）芯片的电迁移阻力，减少空隙形成，提高可靠性。

公开(公告)号：US20120149191A1

公开(公告)日：2012-06-14

申请号：US13398070

申请日：2012-02-16

申请人： Chih-Chao Yang ,  Daniel C. Edelstein

发明人： Chih-Chao Yang ,  Daniel C. Edelstein

IPC分类号： H01L21/768

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.

摘要翻译： 提供了一种互连结构，其具有增强的电迁移可靠性，而不降低电路短产量，并且提高了技术可扩展性。 本发明的互连结构包括具有约3.0或更小的介电常数的电介质材料。 电介质材料具有嵌入其中的至少一种导电材料。 贵金属盖直接位于至少一个导电区域的上表面上。 贵金属帽基本上不延伸到与至少一个导电区域相邻的电介质材料的上表面上，并且贵金属帽材料不会沉积在电介质表面上。 还提供了利用低温（约300℃或更低）化学沉积工艺制造这种互连结构的方法。