公开(公告)号：US20090280631A1

公开(公告)日：2009-11-12

申请号：US12117769

申请日：2008-05-09

Applicant: Jeffrey P. Gambino ,  Michael P. Chudzik ,  Renee T. Mo

Inventor： Jeffrey P. Gambino ,  Michael P. Chudzik ,  Renee T. Mo

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/495 ,  H01L21/28079 ,  H01L21/82345 ,  H01L21/823462 ,  H01L29/4966 ,  H01L29/517

Abstract: The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.

Abstract translation: 本发明在一个实施例中提供了一种形成半导体器件的方法，包括提供包括半导体表面的衬底，该衬底包括第一器件区域和第二器件区域; 在衬底的半导体表面上方形成高k电介质层; 在所述衬底的所述第二器件区域的顶部形成掩模掩模，其中所述衬底的所述第一器件区域被暴露; 在存在于所述衬底的第一器件区域中的高k电介质层的顶部形成第一金属层; 去除所述块掩模以暴露所述衬底的所述第一器件区域中的所述高k电介质层的一部分; 在所述第二器件区域中的所述高k电介质层的所述部分的顶部上形成第二金属层，并且在所述衬底的所述第一器件区域中的所述第一金属顶上形成第二金属层; 以及在所述衬底的所述第一和第二器件区域中形成栅极结构。

公开(公告)号：US07545050B1

公开(公告)日：2009-06-09

申请号：US12183369

申请日：2008-07-31

Applicant: Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Jeffrey P. Gambino ,  David L. Questad

Inventor： Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Jeffrey P. Gambino ,  David L. Questad

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/562 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05655 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A design structure to provide a package for a semiconductor chip that minimizes the stresses and strains that arise from differential thermal expansion in chip to substrate or chip to card interconnections. An improved set of design structure vias above the final copper metallization level that mitigate shocks during semiconductor assembly and testing. Other embodiments include design structures having varying micro-mechanical support structures that further minimize stress and strain in the semiconductor package.

Abstract translation: 提供用于半导体芯片的封装的设计结构，其使从芯片到衬底或芯片到卡互连的差分热膨胀产生的应力和应变最小化。 在最终铜金属化水平之上的一组改进的设计结构通孔，可减轻半导体组装和测试期间的冲击。 其他实施例包括具有变化的微机械支撑结构的设计结构，其进一步最小化半导体封装中的应力和应变。

公开(公告)号：US07521798B2

公开(公告)日：2009-04-21

申请号：US11943277

申请日：2007-11-20

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L23/48

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US20090085152A1

公开(公告)日：2009-04-02

申请号：US11865079

申请日：2007-10-01

Applicant: Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

Inventor： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

IPC: H01L23/62 ,  H01L21/44

CPC classification number: H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.

Abstract translation: 本文提供三维垂直电子熔丝结构及其制造方法。 形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。 该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。 垂直e熔丝结构包括第一接触层和第二接触层。 该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。 当施加电流时，导电材料具有增加的电阻。

公开(公告)号：US07500208B2

公开(公告)日：2009-03-03

申请号：US11673369

申请日：2007-02-09

Applicant: Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

IPC: G06F17/50 ,  G01R31/26

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

Abstract translation: 用于评估半导体集成电路中的线路的新型结构和方法。 在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后，基于所有部分的电阻来确定第一行几何调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

公开(公告)号：US07411135B2

公开(公告)日：2008-08-12

申请号：US10711885

申请日：2004-10-12

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01R12/04

CPC classification number: H01L23/544 ,  H01L22/24 ,  H01L22/32 ,  H01L22/34 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/48 ,  H01L2223/5448 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49227 ,  H01L2224/45099

Abstract: An integrated circuit has a wiring layer below an insulator layer. A pad comprises a conductive material that is on the insulator layer. The pad has a wirebond connection region and a probe pad region. An inspection mark is between the wirebond connection region and the probe pad region. The inspection mark comprises an opening in the insulator layer that is filled with the conductive material. In addition, a contact that is through the insulator layer is adapted to electrically connect the conductor wire in the wiring layer to the pad. The contact is formed of the same conductive material used for the pad and the inspection mark.

Abstract translation: 集成电路在绝缘体层下方具有布线层。 衬垫包括位于绝缘体层上的导电材料。 焊盘具有引线连接区域和探针焊盘区域。 导线连接区域和探针焊盘区域之间的检查标记。 检查标记包括填充有导电材料的绝缘体层中的开口。 此外，穿过绝缘体层的接触件适于将布线层中的导线电连接到焊盘。 接触由用于垫和检查标记的相同的导电材料形成。

公开(公告)号：US07405139B2

公开(公告)日：2008-07-29

申请号：US11462124

申请日：2006-08-03

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L21/322

CPC classification number: H01L29/34 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

Abstract translation: 一种防止在硅（Si）半导体芯片或晶片的后侧形成裂纹的方法。 还提供了一种在电子封装的制造期间，在处理之前和在与基板接合之前，已经形成在硅芯片背面的裂纹扩散的方法。 该方法需要用湿蚀刻处理背面，或者在形成包含芯片或晶片的电子封装之前，在其上施加保护膜层。

公开(公告)号：US20080146040A1

公开(公告)日：2008-06-19

申请号：US12041782

申请日：2008-03-04

Applicant: Jeffrey P. Gambino ,  Thomas L. McDevitt ,  Anthony K. Stamper

Inventor： Jeffrey P. Gambino ,  Thomas L. McDevitt ,  Anthony K. Stamper

IPC: H01L21/31

CPC classification number: C23C16/04 ,  C23C16/513 ,  H01J37/32366

Abstract: A method and an apparatus for performing the method. The method includes: (a) providing an apparatus, wherein the apparatus comprises (i) a chamber, (ii) a plasma device being in and coupled to the chamber, (iii) a shower head being in and coupled to the chamber, and (iv) a chuck being in and coupled to the chamber; (b) placing the substrate on the chuck; (c) using the plasma device to receive a plasma device gas and generate a plasma; (d) directing the plasma at a pre-specified area on the substrate; and (e) using the shower head to receive and distribute a shower head gas in the chamber, wherein the plasma device gas and the shower head gas are selected such that the plasma and the shower head gas when mixed with each other result in a chemical reaction that forms a film at the pre-specified area on the substrate.

Abstract translation: 一种用于执行该方法的方法和装置。 该方法包括：（a）提供一种设备，其中所述设备包括（i）室，（ii）位于室中并耦合到所述室的等离子体设备，（iii）淋浴喷头位于并联接到所述室，以及 （iv）卡盘位于并联接到所述腔室; （b）将基板放置在卡盘上; （c）使用等离子体装置接收等离子体装置气体并产生等离子体; （d）将等离子体引导到基板上的预定区域; 以及（e）使用所述淋浴头来接收和分配所述腔室中的淋浴头气体，其中所述等离子体装置气体和所述喷淋头气体被选择为使得当彼此混合时所述等离子体和所述淋浴头气体产生化学物质 在基板上的预定区域形成膜的反应。

公开(公告)号：US20080122037A1

公开(公告)日：2008-05-29

申请号：US11462124

申请日：2006-08-03

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L29/34 ,  H01L21/66

CPC classification number: H01L29/34 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

Abstract translation: 一种防止在硅（Si）半导体芯片或晶片的后侧形成裂纹的方法。 还提供了一种在电子封装的制造期间，在处理之前和在与基板接合之前，已经形成在硅芯片背面的裂纹扩散的方法。 该方法需要用湿蚀刻处理背面，或者在形成包含芯片或晶片的电子封装之前，在其上施加保护膜层。

公开(公告)号：US20080099877A1

公开(公告)日：2008-05-01

申请号：US11553176

申请日：2006-10-26

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/5258 ,  H01L23/5254 ,  H01L23/5256 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure.

Abstract translation: 导体填充的损伤传播屏障形成为延伸到保险丝和相邻电路元件之间的低k电介质层，以防止在保险丝熔断操作期间传播损坏。 填充损伤传播屏障的导体材料由与用于形成互连结构的导体层相同的导体层形成。