公开(公告)号：US09269629B2

公开(公告)日：2016-02-23

申请号：US14528830

申请日：2014-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Tenko Yamashita

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L27/02

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/26506 ,  H01L21/26566 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/6681 ,  H01L29/78

Abstract: FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC).

公开(公告)号：US09251979B2

公开(公告)日：2016-02-02

申请号：US14010945

申请日：2013-08-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu ,  Zhen Zhang

IPC: G01N27/404 ,  H01H29/02 ,  G01N33/00 ,  G01N15/10 ,  G01N27/327 ,  G01N27/447

CPC classification number: H01H29/02 ,  G01N15/1031 ,  G01N27/3278 ,  G01N27/404 ,  G01N27/44795 ,  G01N33/0009 ,  Y10T29/49117

Abstract: Electromechanical sensors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical sensor includes the following steps. A back gate is formed on a substrate. A gate dielectric is deposited over the back gate. An intermediate layer is formed on the back gate having a micro-fluidic channel formed therein. Top electrodes are formed above the micro-fluidic channel. One or more Janus components are placed in the micro-fluidic channel, wherein each of the Janus components has a first portion having an electrically conductive material and a second portion having an electrically insulating material. The micro-fluidic channel is filled with a fluid. The electrically insulating material has a negative surface charge at a pH of the fluid and an isoelectric point at a pH less than the pH of the fluid.

公开(公告)号：US09240497B2

公开(公告)日：2016-01-19

申请号：US14167499

申请日：2014-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kerber

IPC: H01L21/338 ,  H01L29/812 ,  H01L29/66 ,  H01L29/78 ,  H01L29/808

CPC classification number: H01L29/812 ,  H01L21/84 ,  H01L21/845 ,  H01L27/098 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66848 ,  H01L29/66893 ,  H01L29/785 ,  H01L29/808

Abstract: A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).

公开(公告)号：US09236480B2

公开(公告)日：2016-01-12

申请号：US14044120

申请日：2013-10-02

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed includes, among other things, forming a raised isolation post structure between first and second fins, wherein the raised isolation post structure partially defines first and second spaces between the first and second fins, respectively, and forming a gate structure around the first and second fins and the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces. One illustrative device includes, among other things, first and second fins, a raised isolation post structure positioned between the first and second fins, first and second spaces defined by the fins and the raised isolation post structure, and a gate structure positioned around a portion of the fins and the isolation post structure.

Abstract translation: 所公开的一种方法包括在第一和第二散热片之间形成凸起的隔离柱结构，其中所述凸起的隔离柱结构分别部分地限定所述第一和第二鳍之间的第一和第二空间，并且形成围绕所述第一和第二鳍的栅极结构 和第二鳍片和凸起的隔离柱结构，其中栅极结构的至少一部分位于第一和第二空间中。 一个说明性装置尤其包括第一和第二散热片，位于第一和第二散热片之间的凸起的隔离柱结构，由翅片和凸起的隔离柱结构限定的第一和第二空间以及围绕一部分 的翅片和隔离柱结构。

公开(公告)号：US09228994B1

公开(公告)日：2016-01-05

申请号：US14452741

申请日：2014-08-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L29/40 ,  G01N33/487 ,  H01L27/088 ,  H01L29/66 ,  H01L29/41

CPC classification number: G01N27/4145 ,  G01N33/48721 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/413

Abstract: A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string.

Abstract translation: 可以通过在基板上形成相互间隔一定距离的一对半导体翅片来制造纳米尺寸的电极装置。 该对半导体散热片可以用作一对电极，该电极可被偏置以检测通过纳米尺度串的通过的漏电流。 在一对半导体鳍片之间形成具有均匀间隔距离的纳米通道。 纳米通道可以由形成在一对半导体鳍片上的一对凸起的有源区域之间或在该对半导体鳍片的近侧壁之间的间隙限定。 通过在纳米通道的区域下方的衬底的部分形成开口，以使得能够通过纳米级的串。

公开(公告)号：US09224607B2

公开(公告)日：2015-12-29

申请号：US14029896

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

IPC: H01L27/146 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/28 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/66628

Abstract: A semiconductor device includes a first device region and second device region of opposite polarity. Each device region includes at least a transistor device and associated epitaxy. A high-k barrier is formed to overlay the first device region epitaxy only. The high-k barrier may include a substantially horizontal portion formed upon a top surface of the first device region epitaxy and a substantially vertical portion formed upon an outer surface of the first device region epitaxy. The substantially vertical portion may partially isolate the first device region from the second device region.

Abstract translation: 半导体器件包括具有相反极性的第一器件区域和第二器件区域。 每个器件区域至少包括晶体管器件和相关联的外延。 形成高k屏障以仅覆盖第一器件区域外延。 高k屏障可以包括形成在第一器件区域外延的顶表面上的基本上水平的部分和形成在第一器件区域外延的外表面上的基本上垂直的部分。 基本上垂直的部分可以将第一器件区域与第二器件区域部分隔离。

公开(公告)号：US09219114B2

公开(公告)日：2015-12-22

申请号：US13940280

申请日：2013-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Eric C. Harley ,  Terence B. Hook ,  Ali Khakifirooz ,  Henry K. Utomo ,  Reinaldo A. Vega

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/785

Abstract: A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions.

Abstract translation: 形成由半导体层的顶表面悬挂并由栅极结构支撑的半导体鳍片。 在半导体层的顶表面和栅极结构之间形成绝缘体层。 形成栅极间隔物，通过各向异性蚀刻去除半导体鳍片的物理暴露部分。 随后，可以用锥形蚀刻绝缘体层的物理暴露部分。 或者，可以在绝缘体层的各向异性蚀刻之前形成一次性间隔件。 跨过栅极结构的电介质层中的两个开口之间的横向距离大于栅极间隔物的外侧壁之间的横向距离。 可以进行半导体材料的选择性沉积以形成凸起的活性区域。

公开(公告)号：US09190411B2

公开(公告)日：2015-11-17

申请号：US13914808

申请日：2013-06-11

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Steven John Bentley ,  Murat Kerem Akarvardar ,  Jody Alan Fronheiser ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 一组高迁移率通道散热片形成在逆向掺杂层上，该组高迁移率通道散热片中的每一个包括高迁移率通道材料（例如硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和一组高迁移率通道翅片之间的碳衬垫，以防止载流子溢出到高迁移率通道翅片。

公开(公告)号：US20150249036A1

公开(公告)日：2015-09-03

申请号：US14195484

申请日：2014-03-03

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/768 ,  H01L23/532 ,  H01L27/088

CPC classification number: H01L27/088 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure.

Abstract translation: 本文公开的一个示例涉及将源极/漏极导电触点形成到第一和第二源极/漏极区域，第一源极/漏极区域位于具有第一栅极间距尺​​寸的第一对晶体管器件之间，第二源极/漏极区域被定位 在具有大于第一栅极间距尺​​寸的第二栅极间距尺​​寸的第二对晶体管器件之间，其中第一和第二对晶体管器件具有栅极结构和邻近栅极结构定位的侧壁间隔物。

公开(公告)号：US20150140761A1

公开(公告)日：2015-05-21

申请号：US14599873

申请日：2015-01-19

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/266 ,  H01L21/02

CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。