公开(公告)号：US20180166555A1

公开(公告)日：2018-06-14

申请号：US15880716

申请日：2018-01-26

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Roland Rupp ,  Hans-Joachim Schulze

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/66068 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/402 ,  H01L29/408 ,  H01L29/417 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device may include a semiconductor body of silicon carbide (SiC) and a field effect transistor. The field effect transistor has the semiconductor body that includes a drift region. A polycrystalline silicon layer is formed over or on the semiconductor body, wherein the polycrystalline silicon layer has an average particle size in the range of 10 nm to 5 μm, and includes a source region and a body region. Furthermore, the field effect transistor includes a layer adjacent to the body region gate structure.

公开(公告)号：US20180138301A1

公开(公告)日：2018-05-17

申请号：US15854478

申请日：2017-12-26

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0607 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7813

Abstract: A power semiconductor transistor includes a trench extending into a semiconductor body along a vertical direction and having first and second trench sidewalls and a trench bottom, an electrode in the trench electrically insulated from the semiconductor body, drift and source regions of a first conductivity type, a semiconductor channel region of a second conductivity type laterally adjacent the first trench sidewall and separating the source and drift regions, and a guidance zone. The guidance zone includes a bar section of the second conductivity type extending along the second trench sidewall or along a sidewall of another trench in the vertical direction to a depth in the semiconductor body deeper than the trench bottom, and a plateau section of the second conductivity type adjoining the bar section and extending under the trench bottom towards the semiconductor channel region. The plateau section has at least one opening below the channel region.

公开(公告)号：US20180006115A1

公开(公告)日：2018-01-04

申请号：US15635300

申请日：2017-06-28

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Christian Philipp Sandow ,  Franz-Josef Niedernostheide

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/739 ,  H01L29/10 ,  H01L29/423 ,  H01L29/417 ,  H01L29/36

CPC classification number: H01L29/0696 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/7395 ,  H01L29/7802

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, first and second cells electrically connected to the first load terminal structure and to a drift region, the drift region having a first conductivity type; a first mesa in the first cell and including: a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region; a second mesa in the second cell and including: a port region of the opposite conductivity type and electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure. The insulation structure houses a control electrode structure, and a guidance electrode arranged between the mesas.

公开(公告)号：US20180005830A1

公开(公告)日：2018-01-04

申请号：US15634406

申请日：2017-06-27

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Anton Mauder ,  Roland Rupp ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: H01L21/263 ,  H01L29/78 ,  H01L29/739 ,  H01L29/423 ,  H01L21/67 ,  H01L21/04 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/266 ,  H01L21/265 ,  H01L29/812 ,  H01L29/40

CPC classification number: H01L21/2633 ,  H01L21/047 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28114 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/67069 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/8128

Abstract: By directing an ion beam with a beam divergence θ on a process surface of a semiconductor substrate, parallel electrode trenches are formed in the semiconductor substrate. A center axis of the directed ion beam is tilted to a normal to the process surface at a tilt angle α, wherein at least one of the tilt angle α and the beam divergence θ is not equal to zero. The semiconductor substrate is moved along a direction parallel to the process surface during formation of the electrode trenches. A conductive electrode is formed in the electrode trenches, wherein first sidewalls of the electrode trenches are tilted to the normal by a first slope angle φ 1 with φ 1=(α+0/2) and second sidewalls are tilted to the normal by a second slope angle φ 2 with φ 2=(α−θ/2).

公开(公告)号：US20170170264A1

公开(公告)日：2017-06-15

申请号：US15374012

申请日：2016-12-09

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Wolfgang Bergner ,  Jens Peter Konrath ,  Dethard Peters ,  Reinhold Schoerner

IPC: H01L29/06 ,  H01L29/872 ,  H01L27/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/16 ,  H01L29/808

Abstract: A semiconductor device includes a plurality of drift regions of a plurality of field effect transistor structures arranged in a semiconductor substrate. The plurality of drift regions has a first conductivity type. The semiconductor device further includes a plurality of compensation regions arranged in the semiconductor substrate. The plurality of compensation regions has a second conductivity type. Each drift region of the plurality of drift regions is arranged adjacent to at least one compensation region of the plurality of compensation regions. The semiconductor device further includes a Schottky diode structure or metal-insulation-semiconductor gated diode structure arranged at the semiconductor substrate.

公开(公告)号：US09583578B2

公开(公告)日：2017-02-28

申请号：US13754957

申请日：2013-01-31

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Anton Mauder ,  Franz Hirler

IPC: H01L21/12 ,  H01L29/66 ,  H01L29/36 ,  H01L21/04 ,  H01L29/739 ,  H01L29/861 ,  H01L29/08 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/36 ,  H01L21/04 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611

Abstract: A semiconductor portion of a semiconductor device includes a semiconductor layer with a drift zone of a first conductivity type and at least one impurity zone of a second, opposite conductivity type. The impurity zone adjoins a first surface of the semiconductor portion in an element area. A connection layer directly adjoins the semiconductor layer opposite to the first surface. At a distance to the first surface an overcompensation zone is formed in an edge area that surrounds the element area. The overcompensation zone and the connection layer have opposite conductivity types. In a direction vertical to the first surface, a portion of the drift zone is arranged between the first surface and the overcompensation zone. In case of locally high current densities, the overcompensation zone injects charge carriers into the semiconductor layer that locally counter a further increase of electric field strength and reduce the risk of avalanche breakdown.

Abstract translation: 半导体器件的半导体部分包括具有第一导电类型的漂移区和具有第二相反导电类型的至少一个杂质区的半导体层。 杂质区在元件区域中邻接半导体部分的第一表面。 连接层直接邻接与第一表面相对的半导体层。 在距离第一表面的距离处，在围绕元件区域的边缘区域中形成过度补偿区域。 过补偿区和连接层具有相反的导电类型。 在垂直于第一表面的方向上，漂移区的一部分布置在第一表面和过补偿区之间。 在局部高电流密度的情况下，过补偿区将电荷载流子注入到半导体层中，其局部地抵消电场强度的进一步增加并降低雪崩击穿的风险。

公开(公告)号：US20160226477A1

公开(公告)日：2016-08-04

申请号：US14963509

申请日：2015-12-09

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber ,  Anton Mauder ,  Carsten Schaeffer

IPC: H03K17/12 ,  H01L29/06 ,  H01L29/739

CPC classification number: H03K17/127 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397 ,  H03K3/01 ,  H03K17/66

Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.

Abstract translation: 根据方法的实施例，半导体器件在正向偏置模式中处于截止状态之前，以反向偏置单极模式工作。半导体器件包括至少一个浮置寄生区域，该浮置寄生区域设置在 装置。

公开(公告)号：US20160104780A1

公开(公告)日：2016-04-14

申请号：US14975565

申请日：2015-12-18

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Hans-Joachim Schulze ,  Hans-Joerg Timme ,  Franz Hirler ,  Francisco Javier Santos Rodriguez

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/04 ,  H01L21/3065 ,  H01L21/324 ,  H01L29/45 ,  H01L21/78 ,  H01L21/306

CPC classification number: H01L29/2003 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/306 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/78 ,  H01L29/045 ,  H01L29/45 ,  H01L29/7846 ,  H01L29/7848

Abstract: In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer.

Abstract translation: 在一个实施例中，形成半导体器件的方法包括在衬底的顶表面上形成第一多孔半导体层。 在第一多孔半导体层上形成第一外延层。 在第一外延层内和上方形成电路。 在不完全氧化第一外延层的情况下形成电路。

公开(公告)号：US20160056251A1

公开(公告)日：2016-02-25

申请号：US14814758

申请日：2015-07-31

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Anton Mauder ,  Matteo Dainese ,  Franz Hirler ,  Christian Jaeger ,  Maximillian Roesch ,  Wolfgang Roesner ,  Martin Stiftinger ,  Robert Strenz

IPC: H01L29/423 ,  H01L29/792 ,  H01L27/02 ,  H01L27/115 ,  H01L27/06

CPC classification number: H01L29/42344 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0619 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42376 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7883 ,  H01L29/792

Abstract: A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn junctions with body zones. A second load terminal is electrically connected to a drain construction that forms second pn junctions with the body zones. Control structures, which include a control electrode and charge storage structures, directly adjoin the body zones. The control electrode controls a load current through the body zones. The charge storage structures insulate the control electrode from the body zones and contain a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load electrode.

Abstract translation: 半导体开关器件包括电连接到晶体管单元的源极区的第一负载端子。 源区与身体区形成第一个pn结。 第二负载端子电连接到与主体区域形成第二pn结的排水构造。 包括控制电极和电荷存储结构的控制结构直接与身体区相邻。 控制电极控制穿过身体区域的负载电流。 电荷存储结构将控制电极与体区绝缘，并且在控制电极和第一负载电极之间没有电位差的情况下，包含适于在体区中诱导反转通道的控制电荷。

公开(公告)号：US20160049296A1

公开(公告)日：2016-02-18

申请号：US14920379

申请日：2015-10-22

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Markus Zundel ,  Anton Mauder ,  Andreas Meiser ,  Franz Hirler ,  Hans Weber

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L21/02258 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02299 ,  H01L21/02345 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/32105 ,  H01L29/66325 ,  H01L29/66477

Abstract: A method for forming a semiconductor device includes carrying out an anodic oxidation of a surface region of a semiconductor substrate to form an oxide layer at a surface of the semiconductor substrate by generating an attracting electrical field between the semiconductor substrate and an external electrode within an electrolyte to attract oxidizing ions of the electrolyte, causing an oxidation of the surface region of the semiconductor substrate. Further, the method includes reducing the number of remaining oxidizing ions within the oxide layer, while the semiconductor substrate is within an electrolyte.

Abstract translation: 一种形成半导体器件的方法包括：通过在半导体衬底和半导体衬底内的外部电极之间产生吸引电场，在半导体衬底的表面上进行半导体衬底的表面区域的阳极氧化以形成氧化物层 以吸引电解质的氧化离子，引起半导体衬底的表面区域的氧化。 此外，该方法包括减少氧化物层内剩余氧化离子的数量，同时半导体衬底在电解质内。