公开(公告)号：US20190393356A1

公开(公告)日：2019-12-26

申请号：US16016381

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Van H. LE ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Miriam RESHOTKO ,  Matthew METZ ,  Yih WANG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Tahir GHANI ,  Nazila HARATIPOUR ,  Abhishek SHARMA ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L27/108 ,  H01L23/522 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190103486A1

公开(公告)日：2019-04-04

申请号：US16099532

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Benjamin CHU-KUNG ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L23/31 ,  H01L23/29

Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.

公开(公告)号：US20170263708A1

公开(公告)日：2017-09-14

申请号：US15605795

申请日：2017-05-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L29/06 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02 ,  H01L21/225 ,  H01L21/283 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/20

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20170012125A1

公开(公告)日：2017-01-12

申请号：US15119345

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Van H. LE ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Ravi PILLARISETTY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Robert S. CHAU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823885 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

Abstract translation: 描述用于制造垂直半导体器件和纵向半导体器件的纵横比捕获（ART）方法。 例如，半导体器件包括具有第一晶格常数的最上表面的衬底。 第一源极/漏极区域设置在衬底的最上表面上并且具有第二不同的晶格常数。 垂直沟道区域设置在第一源极/漏极区域上。 第二源极/漏极区域设置在垂直沟道区域上。 栅堆叠设置在垂直沟道区的一部分上并完全环绕。

公开(公告)号：US20160276440A1

公开(公告)日：2016-09-22

申请号：US15037296

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Uygar E. Avci ,  Roza KOTLYAR ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Ian A. YOUNG

IPC: H01L29/12 ,  H01L29/205 ,  H01L29/165 ,  G11C5/06 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/125 ,  G11C5/06 ,  H01L29/0669 ,  H01L29/165 ,  H01L29/205 ,  H01L29/7391 ,  H01L29/7831

Abstract: Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage.

Abstract translation: 本文所述的本发明的实施例包括具有漏极区域，具有与漏极区域相反的导电类型的源极区域的沟道场效应晶体管（TFET），设置在源极区域和漏极区域之间的沟道区域，栅极设置在 沟道区域和设置在源区域和沟道区域的结点附近的异质袋。 异质袋包括不同于沟道区的半导体材料，并且包括小于沟道区中的带隙的隧穿势垒，并且在施加到栅极的电压时在通道区中形成量子阱以增加通过TFET晶体管的电流 门高于阈值电压。

公开(公告)号：US20160211263A1

公开(公告)日：2016-07-21

申请号：US14915185

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Niti GOEL ,  Robert S. CHAU ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Nancy M. ZELICK ,  Gilbert DEWEY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Ravi PILLARISETTY ,  Sansaptak DASGUPTA

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/205 ,  H01L21/8238 ,  H01L21/8252 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

Abstract translation: 从形成在浅沟槽隔离（STI）区域之间的一个或一对沟槽的底部的衬底表面外延生长单个鳍或一对共同组合的n型和p型单晶电子器件鳍。 翅片或翅片被图案化并且STI区域被蚀刻以形成在STI区域的蚀刻顶表面之上延伸的翅片或翅片的高度。 翅片高度可以是其宽度的至少1.5倍。 暴露的侧壁表面和每个翅片的顶表面用一个或多个共形外延材料外延包层以在翅片上形成器件层。 在生长翅片之前，可以从衬底表面生长毯式缓冲外延材料; 并且生长在STI沟槽中的翅片形成在覆盖层上方。 翅片的这种形成减少了材料界面晶格失配的缺陷。

公开(公告)号：US20160204263A1

公开(公告)日：2016-07-14

申请号：US14914906

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Niloy MUKHERJEE ,  Marko RADOSAVLJEVIC ,  Jack T. KAVALIEROS ,  Ravi PILLARISETTY ,  Niti GOEL ,  Van H. LE ,  Gilbert DEWEY ,  Benjamin CHU-KUNG

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.

Abstract translation: 一种包括半导体本体的装置，包括沟道区和设置在沟道区的相对侧上的结区，所述半导体本体包括包括第一带隙的第一材料; 以及包括第二材料的多个纳米线，所述第二材料包括不同于所述第一带隙的第二带隙，所述多个纳米线设置在穿过所述第一材料的分开的平面中，使得所述第一材料围绕所述多个纳米线中的每一个; 以及设置在通道区域上的栅极堆叠。 一种方法，包括在衬底上方的分开的平面中形成多个纳米线，所述多个纳米线中的每一个包括包括第一带隙的材料; 在所述多个纳米线的每一个周围分别形成包层材料，所述包层材料包括第二带隙; 聚结包层材料; 并在所述包层材料上设置栅极叠层。

公开(公告)号：US20160204208A1

公开(公告)日：2016-07-14

申请号：US14778574

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Niti GOEL ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Robert S. CHAU

IPC: H01L29/205 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L29/0607 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/785

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

Abstract translation: 第一种基于III-V材料的缓冲层沉积在硅衬底上。 第二个III-V材料的缓冲层沉积在第一个III-V材料的缓冲层上。 在基于第二III-V材料的缓冲层上沉积基于III-V材料的器件沟道层。

公开(公告)号：US20160181085A1

公开(公告)日：2016-06-23

申请号：US14908112

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Robert S. CHAU

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L21/0243 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/8258 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787

Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.

Abstract translation: 绝缘层被共形沉积在衬底上的沟槽中的多个台面结构上。 绝缘层填充台面结构外部的空间。 成核层沉积在台面结构上。 III-V材料层沉积在成核层上。 在绝缘层上横向生长III-V材料层。