公开(公告)号：US20190164808A1

公开(公告)日：2019-05-30

申请号：US15859286

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Michael L. HATTENDORF ,  Curtis WARD ,  Heidi M. MEYER ,  Tahir GHANI ,  Christopher P. AUTH

IPC: H01L21/762 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.

公开(公告)号：US20190139957A1

公开(公告)日：2019-05-09

申请号：US16098084

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Biswajeet GUHA ,  Tahir GHANI ,  Christopher N. KENYON ,  Leonard P. GULER

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/535

Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.

公开(公告)号：US20190036010A1

公开(公告)日：2019-01-31

申请号：US16072301

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Brian MAERTZ ,  Christopher J. WIEGAND ,  Daniel G. OEULLETTE ,  MD Tofizur RAHMAN ,  Oleg GOLONZKA ,  Justin S. BROCKMAN ,  Tahir GHANI ,  Brian S. DOYLE ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Kaan OGUZ

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.

公开(公告)号：US20190027679A1

公开(公告)日：2019-01-24

申请号：US16070415

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Daniel G. OUELLETTE ,  Christopher J. WIEGAND ,  MD Tofizur RAHMAN ,  Brian MAERTZ ,  Oleg GOLONZKA ,  Justin S. BROCKMAN ,  Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Kaan OGUZ ,  Tahir GHANI ,  Mark L. DOCZY

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10

Abstract: Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs), and the resulting structures, are described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer is disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer. The ILD layer has an uppermost surface co-planar or substantially co-planar with an uppermost surface of the lateral strain-inducing material layer.

公开(公告)号：US20180204932A1

公开(公告)日：2018-07-19

申请号：US15570965

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Partick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L27/108

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/78 ,  H01L29/785

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20180158930A1

公开(公告)日：2018-06-07

申请号：US15867210

申请日：2018-01-10

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Michael L. HATTENDORF ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848 ,  H01L29/785

Abstract: Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.

公开(公告)号：US20180151702A1

公开(公告)日：2018-05-31

申请号：US15576251

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Gopinath BHIMARASETTI ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Anand S. MURTHY ,  Rishabh MEHANDRU

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/02546 ,  H01L23/49827 ,  H01L23/49838 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.

公开(公告)号：US20180145077A1

公开(公告)日：2018-05-24

申请号：US15574820

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Anand S. MURTHY ,  Tahir GHANI ,  Willy RACHMADY ,  Chandra S. MOHAPATRA ,  Jack T. KAVALIEROS ,  Glenn A. GLASS

IPC: H01L27/092 ,  H01L29/205 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/8258 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.

公开(公告)号：US20180047808A1

公开(公告)日：2018-02-15

申请号：US15789315

申请日：2017-10-20

Applicant: Intel Corporation

Inventor： Milton Clair WEBB ,  Mark BOHR ,  Tahir GHANI ,  Szuya S. LIAO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L27/092 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L29/0649 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

公开(公告)号：US20170317187A1

公开(公告)日：2017-11-02

申请号：US15528793

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia RAHHAL-ORABI ,  Nancy M. ZELICK ,  Marc C. FRENCH ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/66742 ,  B82Y10/00 ,  H01L21/02392 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: An embodiment includes a device comprising: first and second fins adjacent one another and each including channel and subfin layers, the channel layers having bottom surfaces directly contacting upper surfaces of the subfin layers; wherein (a) the bottom surfaces are generally coplanar with one another and are generally flat; (b) the upper surfaces are generally coplanar with one another and are generally flat; and (c) the channel layers include an upper material and the subfin layers include a lower III-V material different from the upper III-V material. Other embodiments are described herein.