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公开(公告)号：US20180197792A1
公开(公告)日：2018-07-12
申请号：US15404466
申请日：2017-01-12
发明人： Dechao Guo , Zuoguang Liu , Gen Tsutsui , Heng Wu
IPC分类号： H01L21/8238 , H01L27/092 , H01L21/8234 , H01L29/165 , H01L29/10 , H01L21/265 , H01L21/324
CPC分类号： H01L21/823821 , H01L21/26513 , H01L21/324 , H01L21/823437 , H01L27/0924 , H01L29/1033 , H01L29/165 , H01L29/41791 , H01L29/785 , H01L29/7851
摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method includes forming a first semiconductor fin in a first region of a substrate and a second semiconductor fin in a second region of the substrate. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a first channel region of the second semiconductor fin. A first doped region is formed on the first semiconductor fin, adjacent to the first gate. A second doped region is formed in a top portion of the first doped region and a third doped region is formed in a top portion of the second semiconductor fin. The third doped region is removed to form a recess and the recess is filled with a fourth doped region.
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公开(公告)号：US11942557B2
公开(公告)日：2024-03-26
申请号：US17246762
申请日：2021-05-03
发明人： Lan Yu , Andrew M. Greene , Wenyu Xu , Heng Wu
IPC分类号： H01L29/786 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/0665 , H01L29/41775 , H01L29/42392 , H01L29/66545
摘要： A semiconductor nanosheet device including semiconductor channel layers vertically aligned and stacked one on top of another, separated by a work function metal, and a second layer between two first layers, the second layer and two first layers between the semiconductor channel layers and a substrate. A semiconductor device including a lower first layer, a second layer, and a source drain region between a first set of semiconductor channel layers vertically aligned and stacked one on top of another, and a second set of semiconductor channel layers. A method including forming a stack sacrificial layer, a stack of nanosheet layers, forming a cavity by removing the stack sacrificial layer, and simultaneously forming a first layer on an upper surface of the stack sacrificial layer, on vertical side surfaces of the set of sacrificial gates, and an upper first layer and a lower first layer in a portion of the cavity.
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公开(公告)号：US20240096887A1
公开(公告)日：2024-03-21
申请号：US17945422
申请日：2022-09-15
发明人： Ruqiang Bao , Dechao Guo , Junli Wang , Heng Wu
IPC分类号： H01L27/092 , H01L21/02 , H01L21/321 , H01L21/822 , H01L21/8238 , H01L23/528 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/78
CPC分类号： H01L27/0922 , H01L21/02532 , H01L21/02603 , H01L21/3212 , H01L21/8221 , H01L21/823807 , H01L21/823857 , H01L21/823871 , H01L23/5286 , H01L29/0673 , H01L29/401 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/6684 , H01L29/775 , H01L29/78391
摘要： A semiconductor device includes a substrate; a set of first transistors positioned on an upper surface of the substrate, each of the set of first transistors comprising a first gate and a first dielectric; an insulating layer positioned on an upper surface of the set of first transistors; and a set of second transistors positioned over the set of first transistors and with the set of first transistors on an upper surface of the insulating layer, each of the set of second transistors having a second gate and a second dielectric; wherein each of the first dielectrics is connected to a sidewall of each of a corresponding first gate; and wherein each of the second dielectrics is connected to the insulating layer.
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公开(公告)号：US20240079476A1
公开(公告)日：2024-03-07
申请号：US17902275
申请日：2022-09-02
发明人： Tao Li , Ruilong Xie , Heng Wu , Julien Frougier
IPC分类号： H01L29/66 , H01L21/8234 , H01L23/48 , H01L29/06 , H01L29/417 , H01L29/775 , H01L29/786
CPC分类号： H01L29/66545 , H01L21/823412 , H01L21/823418 , H01L23/481 , H01L29/0673 , H01L29/41733 , H01L29/775 , H01L29/78696
摘要： A method of forming a backside power connection is provided. The method includes forming a plurality of sacrificial contact plugs and a plurality of sacrificial fill regions on a substrate, and forming a source/drain over a first sacrificial contact plug. The method further includes forming a replacement metal gate structure over a first sacrificial fill region, and forming an electrical contact to each of the replacement metal gate structure and the source/drain. The method further includes inverting the plurality of sacrificial contact plugs, source/drain, replacement metal gate structure, and substrate. The method further includes removing the first sacrificial contact plug and the first sacrificial fill region, and forming a first conductive contact to the source/drain and a second conductive contact to the replacement metal gate structure.
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55.发明公开公开(公告)号：US20230420457A1
公开(公告)日：2023-12-28
申请号：US17808360
申请日：2022-06-23
发明人： Julien Frougier , Andrew M. Greene , Shogo Mochizuki , Kangguo Cheng , Ruilong Xie , Heng Wu , Min Gyu Sung , Liqiao Qin , Gen Tsutsui
IPC分类号： H01L27/092 , H01L29/06 , H01L29/786 , H01L29/423 , H01L29/161 , H01L21/8238
CPC分类号： H01L27/0922 , H01L29/0665 , H01L21/823807 , H01L29/42392 , H01L29/161 , H01L29/78696
摘要： Embodiments of the invention include a single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET. A PFET comprising at least one silicon germanium channel is formed. An NFET comprising at least one silicon channel is formed, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction.
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公开(公告)号：US11818971B2
公开(公告)日：2023-11-14
申请号：US17977336
申请日：2022-10-31
发明人： Heng Wu , Ruilong Xie , Nanbo Gong , Cheng-Wei Cheng
CPC分类号： H10N70/8613 , H10B63/00 , H10N70/063 , H10N70/068 , H10N70/231 , H10N70/8828
摘要： Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.
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公开(公告)号：US20230309320A1
公开(公告)日：2023-09-28
申请号：US17656045
申请日：2022-03-23
发明人： Heng Wu , Ruilong Xie , Julien Frougier , Min Gyu Sung , Chen Zhang
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1697 , H01L43/08 , H01L43/14 , H01L43/04
摘要： Embodiments are disclosed for a system. The system includes a semiconductor structure. The semiconductor structure includes a wafer, multiple transistors, and a magnetoresistive random access memory (MRAM) cell disposed on the backside of the wafer. The transistors are disposed on a front end of line (FEOL) of the wafer. The MRAM cell is connected to a source-drain of the transistors by a contact disposed on the backside of the wafer. The transistors are in direct electrical contact with the MRAM cell by at least one contact.
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公开(公告)号：US20230299176A1
公开(公告)日：2023-09-21
申请号：US18324240
申请日：2023-05-26
发明人： Lan Yu , Kangguo Cheng , Heng Wu , Chen Zhang
IPC分类号： H01L29/66 , H01L29/06 , H01L29/08 , H01L29/786 , H01L29/423
CPC分类号： H01L29/66545 , H01L29/0673 , H01L29/0847 , H01L29/78696 , H01L29/42392
摘要： Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.
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公开(公告)号：US11729996B2
公开(公告)日：2023-08-15
申请号：US17444174
申请日：2021-07-30
发明人： Heng Wu , Ruilong Xie , Julien Frougier , Bruce B. Doris
CPC分类号： H10B61/00 , G11C11/161 , G11C11/1675 , H10N50/01 , H10N50/80
摘要： An embedded eMRAM device for eFlash replacement including an MTJ pillar located between a top electrode and a bottom electrode for forming an MRAM array. The bottom electrode is disposed above a substrate and surrounded by a first dielectric spacer, while the top electrode is disposed above the MTJ pillar and surrounded by a second dielectric spacer. A bottom metal plate is disposed on opposing sides of the bottom electrode between first and second dielectric layers and is electrically separated from the bottom electrode by the first dielectric spacer. A top metal plate is disposed on opposing sides of the top electrode between third and fourth dielectric layers and is electrically separated from the top electrode by the second dielectric spacer. A bias voltage applied to the top metal plate and the bottom metal plate generates an external electric field on the MTJ pillar for creating a VCMA effect.
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公开(公告)号：US20230238285A1
公开(公告)日：2023-07-27
申请号：US17648817
申请日：2022-01-25
发明人： Heng Wu , Junli Wang , Teresa J. Wu , Tenko Yamashita
IPC分类号： H01L21/8238 , H01L21/02 , H01L23/50 , H01L25/065 , H01L27/11551
CPC分类号： H01L21/823807 , H01L21/02532 , H01L21/823871 , H01L23/50 , H01L25/0652 , H01L27/11551 , H01L27/11597
摘要： Embodiments of present invention provide a semiconductor device. The semiconductor device includes a silicon (Si) substrate containing a set of short channel field-effect-transistors (FETs); a germanium (Ge) layer on top of the Si substrate containing a set of long channel p-type FETs (PFETs); and an oxide semiconductor layer on top of the Ge layer containing a set of long channel n-type FETs (NFETs), wherein the set of short channel FETs, long channel PFETs, and long channel NFETs are interconnected through a set of far-back-end-of-line (FBEOL) layers.
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