公开(公告)号：US07018504B1

公开(公告)日：2006-03-28

申请号：US09658784

申请日：2000-09-11

Applicant: Ivo Raaijmakers ,  Ravinder Aggarwal ,  James Kusbel

Inventor： Ivo Raaijmakers ,  Ravinder Aggarwal ,  James Kusbel

IPC: C23F1/00 ,  H01L21/306 ,  C23C16/00

CPC classification number: H01L21/67751 ,  H01L21/67167 ,  H01L21/67201 ,  H01L21/67757

Abstract: A wafer carrier adapted to hold a plurality of wafers and is positioned on an elevator plate in a load lock. The elevator plate is adapted to move between a first position with the carrier in a first chamber of the load lock and a second position with the carrier in the auxiliary chamber. In the second position, the elevator plate substantially seals the auxiliary chamber from the first chamber. In use, a first wafer is placed onto the wafer carrier. The wafer carrier can moved into the auxiliary chamber before or after the first wafer is placed onto the wafer carrier. The first wafer is auxiliary processed in the auxiliary chamber. A second wafer is placed onto the wafer carrier. Preferably after the second wafer is placed onto the wafer carrier, the first wafer is removed from the load lock. A third wafer is preferably then placed onto the wafer carrier so that the second wafer can cool. The second wafer is then removed from the load lock. The cycle is repeated.

Abstract translation: 适于保持多个晶片并且位于加载锁中的电梯板上的晶片载体。 所述升降板适于在所述负载锁的第一室中的所述载体的第一位置和所述辅助室中的所述载体的第二位置之间移动。 在第二位置，升降板基本上将辅助室与第一室密封。 在使用中，将第一晶片放置在晶片载体上。 在将第一晶片放置在晶片载体上之前或之后，晶片载体可以移动到辅助室中。 第一个晶片在辅助室中辅助处理。 将第二晶片放置在晶片载体上。 优选地，在将第二晶片放置在晶片载体上之后，将第一晶片从负载锁上移除。 然后优选将第三晶片放置在晶片载体上，使得第二晶片可以冷却。 然后将第二个晶片从负载锁中取出。 重复循环。

公开(公告)号：US06957690B1

公开(公告)日：2005-10-25

申请号：US09584656

申请日：2000-05-30

Applicant: Ivo Raaijmakers

Inventor： Ivo Raaijmakers

IPC: C23C16/56 ,  F28F7/00 ,  H01L21/00

CPC classification number: H01L21/67109

Abstract: Methods and apparatuses are provided for cooling semiconductor substrates prior to handling. In one embodiment, a substrate and support structure combination is lifted after high temperature processing to a cold wall of a thermal processing chamber, which acts as a heat sink. Conductive heat transfer across a small gap from the substrate to the heat sink speeds wafer cooling prior to handling the wafer (e.g., with a robot). In another embodiment, a separate plate is kept cool within a pocket during processing, and is moved close to the substrate and support after processing. In yet another embodiment, a cooling station between a processing chamber and a storage cassette includes two movable cold plates, which are movable to positions closely spaced on either side of the wafer.

Abstract translation: 提供了用于在处理之前冷却半导体衬底的方法和装置。 在一个实施例中，将衬底和支撑结构组合在高温处理之后提升到用作散热器的热处理室的冷壁。 在从基板到散热片的小间隙处的导电热传递在处理晶片（例如，使用机器人）之前加速晶片冷却。 在另一个实施例中，单独的板在处理期间保持在袋内冷却，并且在处理之后移动靠近基板并支撑。 在另一个实施例中，处理室和存储盒之间的冷却站包括两个可移动的冷板，其可移动到在晶片的任一侧上紧密间隔开的位置。

公开(公告)号：US20050183829A1

公开(公告)日：2005-08-25

申请号：US11095335

申请日：2005-03-21

Applicant: Matthew Goodman ,  Ivo Raaijmakers ,  Loren Jacobs ,  Franciscus van Bilsen ,  Michael Meyer ,  Eric Barrett

Inventor： Matthew Goodman ,  Ivo Raaijmakers ,  Loren Jacobs ,  Franciscus van Bilsen ,  Michael Meyer ,  Eric Barrett

IPC: H01L21/683 ,  C23C16/458 ,  C23C16/48 ,  H01L21/205 ,  H01L21/26 ,  H01L21/687 ,  C23F1/00

CPC classification number: H01L21/68735 ,  C23C16/4581 ,  C23C16/4585 ,  C23C16/481 ,  H01L21/68721 ,  H01L21/68728 ,  H01L21/68785

Abstract: Improvements in the design of a low mass wafer holder are disclosed. The improvements include the use of peripherally located, integral lips to space a wafer or other substrate above the base plate of the wafer holder. A uniform gap is thus provided between the wafer and the base plate, such as will temper rapid heat exchanges, allow gas to flow between the wafer and wafer holder during wafer pick-up, and keep the wafer holder thermally coupled with the wafer. At the same time, thermal disturbance from lip contact with the wafer is reduced. Gas flow during pick-up can be provided through radial channels in a wafer holder upper surface, or through backside gas passages. A thicker ring is provided at the wafer holder perimeter, and is provided in some embodiments as an independent piece to accommodate stresses accompanying thermal gradients. Self-centering mechanisms are provided to keep the wafer holder centered relative to a spider which is subject to differential thermal expansion.

Abstract translation: 公开了一种低质量晶片支架的设计改进。 这些改进包括使用外围定位的整体式唇缘以将晶片或其它基板放置在晶片保持器的基板之上。 因此，在晶片和基板之间提供均匀的间隙，例如将回火快速热交换，允许气体在晶片拾取期间在晶片和晶片保持器之间流动，并保持晶片保持器与晶片热耦合。 同时，与晶片的唇接触的热扰动减小。 拾取期间的气流可以通过晶片保持器上表面中的径向通道或通过背侧气体通道来提供。 在晶片保持器周边处提供较厚的环，并且在一些实施例中作为独立件提供以适应伴随热梯度的应力。 提供自对中机构以保持晶片保持架相对于经受不同热膨胀的蜘蛛座居中。

公开(公告)号：US20050181555A1

公开(公告)日：2005-08-18

申请号：US11106220

申请日：2005-04-13

Applicant: Suvi Haukka ,  Ivo Raaijmakers ,  Wei Li ,  Juhana Kostamo ,  Hessel Sprey ,  Christiaan Werkhoven

Inventor： Suvi Haukka ,  Ivo Raaijmakers ,  Wei Li ,  Juhana Kostamo ,  Hessel Sprey ,  Christiaan Werkhoven

IPC: C23C16/02 ,  C23C16/34 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/48 ,  C30B25/14 ,  H01L21/28 ,  H01L21/285 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L29/51 ,  H01L21/8238

CPC classification number: C23C16/029 ,  C23C16/34 ,  C23C16/401 ,  C23C16/403 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45534 ,  C30B25/14 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/3185 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2221/1089

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.

Abstract translation: 通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。 在所示实施例中，在循环过程中引入了不同量的杂质源。 因此，即使对于非常薄的层也提供了梯度栅极电介质。 薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。 类似地，栅极电介质可以从氧化铝到氧化铝和较高介电材料（例如ZrO 2）的混合物变化为纯高k材料并返回到氧化铝。 在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。 在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。 有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。 在一些实施例中，提供了额外的种子层或附加的过渡层。

公开(公告)号：US20050101132A1

公开(公告)日：2005-05-12

申请号：US10998229

申请日：2004-11-26

Applicant: Ki-Bum Kim ,  Pekka Soininen ,  Ivo Raaijmakers

Inventor： Ki-Bum Kim ,  Pekka Soininen ,  Ivo Raaijmakers

IPC: C23C16/20 ,  C23C16/34 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/28562 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.

公开(公告)号：US06861334B2

公开(公告)日：2005-03-01

申请号：US09887199

申请日：2001-06-21

Applicant: Ivo Raaijmakers ,  Pekka T. Soininen ,  Ernst H. A. Granneman

Inventor： Ivo Raaijmakers ,  Pekka T. Soininen ,  Ernst H. A. Granneman

IPC: H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC classification number: H01L21/02164 ,  H01L21/02145 ,  H01L21/02178 ,  H01L21/02216 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/76224

Abstract: A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no more than about a monolayer of material, capable of completely filling high aspect ratio trenches. Additionally, the trench-fill material composition can be tailored by processes described herein, particularly to match the coefficient of thermal expansion (CTE) to that of the surrounding substrate within which the trench is formed. Mixed phases of mullite and silica have been found to meet the goals of device isolation and matched CTE. The described process includes mixing atomic layer deposition cycles of aluminum oxide and silicon oxide in ratios selected to achieve the desired composition of the isolation material, namely on the order of 30% alumina and 70% silicon oxide by weight.

Abstract translation: 通过原子层沉积形成电介质膜，以保形地填充狭窄的深沟槽，用于器件隔离。 所示实施方案的方法包括交替地以一系列循环脉冲气相反应物，其中每个循环不超过约单层材料，能够完全填充高纵横比沟槽。 此外，沟槽填充材料组合物可以通过本文所述的方法来定制，特别是使热膨胀系数（CTE）与其中形成沟槽的周围基底的热膨胀系数相匹配。 已经发现莫来石和二氧化硅的混合相达到器件隔离和匹配CTE的目标。 所描述的方法包括以选择的比例混合氧化铝和氧化硅的原子层沉积循环，以达到分离材料的所需组成，即按重量计30％氧化铝和70％氧化硅。

公开(公告)号：US06831315B2

公开(公告)日：2004-12-14

申请号：US09791072

申请日：2001-02-22

Applicant: Ivo Raaijmakers ,  Suvi P. Haukka ,  Ernst H. A. Granneman

Inventor： Ivo Raaijmakers ,  Suvi P. Haukka ,  Ernst H. A. Granneman

IPC: H01L27108

CPC classification number: H01L28/40 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/31604 ,  H01L21/3162 ,  H01L21/31691 ,  H01L27/10852 ,  H01L27/10861 ,  H01L28/84 ,  Y10T428/265

Abstract: Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design. Alternately pulsed chemistries are also provided for depositing top electrode materials with continuous coverage of capacitor dielectric, realizing the full capacitance benefits of the underlying textured morphology.

Abstract translation: 提供了用于集成存储器单元的织构化硅电极上的适形电容器电介质的方法和结构。 电容器结构和第一电极或板形成在半导体衬底之上或之内。 第一电极包括用于增加电容器板表面积的半球形晶粒（HSG）硅。 然后将HSG形貌暴露于交替的化学物质以形成所需介电材料的单层。 示例性工艺流程包括注入恒定载流子的交替脉冲的金属有机和氧源气体。 因此，自身端接的金属层与氧气反应。 接近完美的步骤覆盖允许电容器电介质的最小厚度，给定特定材料的泄漏问题，从而使存储器单元的电容最大化，并提高给定存储单元设计的单元可靠性。 还提供了替代脉冲化学物质用于沉积具有电容器电介质的连续覆盖的顶部电极材料，实现了下面的织构形态的全电容益处。

公开(公告)号：US06820570B2

公开(公告)日：2004-11-23

申请号：US10222005

申请日：2002-08-14

Applicant: Olli Kilpela ,  Ville Saanila ,  Wei-Min Li ,  Kai-Erik Elers ,  Juhana Kostamo ,  Ivo Raaijmakers ,  Ernst Granneman

Inventor： Olli Kilpela ,  Ville Saanila ,  Wei-Min Li ,  Kai-Erik Elers ,  Juhana Kostamo ,  Ivo Raaijmakers ,  Ernst Granneman

IPC: C23C16509

CPC classification number: C23C16/45544 ,  C23C16/4412 ,  C23C16/452 ,  C23C16/45514 ,  C23C16/45536 ,  C23C16/45565 ,  C23C16/45589 ,  C23C16/507 ,  C23C16/509

Abstract: Various reactors for growing thin films on a substrate by subjecting the substrate to alternately repeated surface reactions of vapor-phase reactants are disclosed. In one embodiment, the reactor comprises a reaction chamber. A showerhead plate divides the reaction chamber into upper and lower parts. A first precursor is directed towards the lower half of the reaction chamber and a second precursor is directed towards the upper half of the reaction chamber. The substrate is disposed within the lower half of the reaction chamber. The showerhead plate includes plurality passages such that the upper half is in communication with the lower half of the reaction chamber. In another arrangement, the upper half of the reaction chamber defines a plasma cavity in which in-situ radicals are formed. In yet another arrangement, the reaction chamber includes a shutter plate, which is configured to selectively open and close the passages in the showerhead plate. In other arrangements, the showerhead plate is arranged to modify the local flow patterns of the gases flowing through the reaction chamber.

Abstract translation: 公开了用于通过使衬底经历气相反应物的交替重复表面反应而在衬底上生长薄膜的各种反应器。 在一个实施方案中，反应器包括反应室。 喷头板将反应室分成上部和下部。 第一前体指向反应室的下半部分，第二前体指向反应室的上半部分。 基板设置在反应室的下半部内。 喷头板包括多个通道，使得上半部分与反应室的下半部连通。 在另一种布置中，反应室的上半部限定了其中形成原位自由基的等离子体腔。 在另一种布置中，反应室包括挡板，其构造成选择性地打开和关闭喷头板中的通道。 在其他布置中，喷头板被布置成改变流过反应室的气体的局部流动模式。

公开(公告)号：US06764546B2

公开(公告)日：2004-07-20

申请号：US10317275

申请日：2002-12-10

Applicant: Ivo Raaijmakers

Inventor： Ivo Raaijmakers

IPC: C30B2514

CPC classification number: C23C16/45544 ,  C23C16/452 ,  C23C16/45521 ,  C23C16/45536 ,  C23C16/45542 ,  C30B25/14 ,  C30B29/38 ,  H01J37/3244 ,  Y10T117/10

Abstract: An improved apparatus and method for substrate layer deposition in which substrate layers are grown by carrier gas delivery of sequential pulses of reactants to the substrate surface. At least one of the reactants comprises excited species, e.g., radicals. In a specific embodiment, the apparatus of this invention provides sequential repeated pulses of reactants in a flow of carrier gas for reaction at a substrate surface. The reactant pulses are delivered with sufficient intervening delay times to minimize undesirable reaction between reactants in adjacent pulses in the gas phase or undesired uncontrolled reactions on the substrate surface.

Abstract translation: 一种用于衬底层沉积的改进的装置和方法，其中衬底层通过将反应物的顺序脉冲的载气输送到衬底表面而生长。 至少一种反应物包括激发的物质，例如自由基。 在具体实施方案中，本发明的装置在载体气流中提供反应物的顺序重复脉冲，以在基底表面反应。 反应物脉冲以足够的中间延迟时间递送，以使气相中相邻脉冲中的反应物之间的不希望的反应最小化，或者在衬底表面上产生不期望的不受控制的反应。

公开(公告)号：US06703708B2

公开(公告)日：2004-03-09

申请号：US10329658

申请日：2002-12-23

Applicant: Christiaan J. Werkhoven ,  Ivo Raaijmakers ,  Suvi P. Haukka

Inventor： Christiaan J. Werkhoven ,  Ivo Raaijmakers ,  Suvi P. Haukka

IPC: H01L2348

CPC classification number: H01L21/28185 ,  C23C16/029 ,  C23C16/34 ,  C23C16/401 ,  C23C16/403 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45534 ,  C30B25/14 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/3185 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2221/1089 ,  H01L2924/0002 ,  Y10T428/24942 ,  Y10T428/2495 ,  H01L2924/00

Abstract: Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a graded transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

Abstract translation: 通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变化到单层。 在所示实施例中，在循环过程中引入了不同量的杂质源。 因此，即使对于非常薄的层也提供了梯度栅极电介质。 薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。 类似地，栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料（例如，ZrO 2）到纯高k材料并返回到氧化铝的混合物。 在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。 在交替沉积过程中，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成渐变过渡区，直到在上表面形成纯铜。 有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。