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117 条记录 (耗时 0.035 秒)

    Invertable pattern loading with dry etch
    54.
    发明授权
    Invertable pattern loading with dry etch 有权
    用干蚀刻反转图案加载

    公开(公告)号：US08435902B2

    公开(公告)日：2013-05-07

    申请号：US12959155

    申请日：2010-12-02

    申请人： Jing Tang ,  Nitin Ingle ,  Dongqing Yang ,  Shankar Venkataraman

    发明人： Jing Tang ,  Nitin Ingle ,  Dongqing Yang ,  Shankar Venkataraman

    IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  C23F3/00

    CPC分类号： H01L21/31116 ,  H01J37/32091

    摘要： A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench.

    摘要翻译： 描述了从窄沟槽和宽沟槽（或开放区域）中蚀刻氧化硅的方法，其允许宽沟槽中的蚀刻比窄沟槽中的蚀刻进一步进行。 该方法包括两个干蚀刻循环。 第一干蚀刻循环涉及低强度或缩写升华步骤，其在窄沟槽中留下固体残留物。 剩余的固体残余物在第二干蚀刻循环期间抑制窄沟槽中的蚀刻进程，允许宽沟槽中的蚀刻超过窄沟槽中的蚀刻。

    REDUCED PATTERN LOADING USING SILICON OXIDE MULTI-LAYERS
    55.
    发明申请
    REDUCED PATTERN LOADING USING SILICON OXIDE MULTI-LAYERS 有权
    使用硅氧化物多层的减少图案加载

    公开(公告)号：US20120225565A1

    公开(公告)日：2012-09-06

    申请号：US13251621

    申请日：2011-10-03

    申请人： Sidharth Bhatia ,  Paul Edward Gee ,  Shankar Venkataraman

    发明人： Sidharth Bhatia ,  Paul Edward Gee ,  Shankar Venkataraman

    IPC分类号： H01L21/31

    CPC分类号： H01L21/0228 ,  C23C16/402 ,  C23C16/452 ,  C23C16/45523 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/28556

    摘要： Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.

    摘要翻译： 本公开的方面涉及在图案化衬底上沉积适形氧化硅多层的方法。 共形氧化硅多层各自通过沉积多个子层形成。 通过将BIS（二乙基氨基）硅烷（BDEAS）和含氧前体流入处理室来沉积子层，使得在图案化的衬底表面上实现相对均匀的介电生长速率。 等离子体处理可以随后形成亚层，以进一步改善保形性并降低保形氧化硅多层膜的湿蚀刻速率。 根据实施例生长的共形氧化硅多层的沉积对图案密度的依赖性降低，同时仍然适用于非牺牲应用。

    Reduced pattern loading using bis(diethylamino)silane (C8H22N2Si) as silicon precursor
    56.
    发明授权
    Reduced pattern loading using bis(diethylamino)silane (C8H22N2Si) as silicon precursor 失效
    使用双（二乙基氨基）硅烷（C 8 H 22 N 2 Si）作为硅前体的减少图案负载

    公开(公告)号：US08236708B2

    公开(公告)日：2012-08-07

    申请号：US12855877

    申请日：2010-08-13

    申请人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

    发明人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

    IPC分类号： H01L21/316 ,  C23C16/40

    CPC分类号： H01L21/02219 ,  C23C16/401 ,  H01L21/02164 ,  H01L21/02271

    摘要： Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.

    摘要翻译： 本公开的方面涉及在图案化衬底上沉积电介质层的方法。 在实施方案中，通过将BIS（二乙胺）硅烷（BDEAS），臭氧和分子氧流入处理室来沉积电介质层，使得跨越图案化的衬底表面实现相对均匀的电介质生长速率。 根据实施例生长的电介质层的沉积可以减少对图案密度的依赖性，同时仍然适用于非牺牲应用。

    LOADLOCK BATCH OZONE CURE
    57.
    发明申请
    LOADLOCK BATCH OZONE CURE 有权

    公开(公告)号：US20120145079A1

    公开(公告)日：2012-06-14

    申请号：US13161371

    申请日：2011-06-15

    申请人： Dmitry Lubomirsky ,  Jay D. Pinson, II ,  Kirby H. Floyd ,  Adib Khan ,  Shankar Venkataraman

    发明人： Dmitry Lubomirsky ,  Jay D. Pinson, II ,  Kirby H. Floyd ,  Adib Khan ,  Shankar Venkataraman

    IPC分类号： C23C16/458

    CPC分类号： H01L21/67178 ,  H01L21/67109 ,  H01L21/6719 ,  H01L21/67757

    摘要： A substrate processing chamber for processing a plurality of wafers in batch mode. In one embodiment the chamber includes a vertically aligned housing having first and second processing areas separated by an internal divider, the first processing area positioned directly over the second processing area; a multi-zone heater operatively coupled to the housing to heat the first and second processing areas independent of each other; a wafer transport adapted to hold a plurality of wafers within the processing chamber and move vertically between the first and second processing areas; a gas distribution system adapted to introduce ozone into the second area and steam into the first processing area; and a gas exhaust system configured to exhaust gases introduced into the first and second processing areas.

    摘要翻译： 一种用于以批处理模式处理多个晶片的衬底处理室。 在一个实施例中，所述腔室包括具有由内部分隔器隔开的第一和第二处理区域的垂直排列的壳体，所述第一处理区域直接位于所述第二处理区域上方; 多区加热器，其可操作地耦合到所述壳体以彼此独立地加热所述第一处理区域和所述第二处理区域; 晶片传送器，其适于将多个晶片保持在处理室内并在第一和第二处理区域之间垂直移动; 气体分配系统，其适于将臭氧引入所述第二区域并将蒸汽引入到所述第一处理区域中; 以及排气系统，其被配置为排出引入到第一和第二处理区域中的气体。

    METHODS FOR FORMING LOW STRESS DIELECTRIC FILMS
    58.
    发明申请
    METHODS FOR FORMING LOW STRESS DIELECTRIC FILMS 审中-公开
    形成低应力电介质膜的方法

    公开(公告)号：US20120015113A1

    公开(公告)日：2012-01-19

    申请号：US12835574

    申请日：2010-07-13

    申请人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Shankar Venkataraman

    发明人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Shankar Venkataraman

    IPC分类号： C23C16/513

    CPC分类号： C23C16/513 ,  C23C16/401 ,  C23C16/44

    摘要： A method for forming a multi-layer silicon oxide film on a substrate includes performing a deposition cycle that comprises depositing a silicon oxide layer using a thermal chemical vapor deposition (CVD) process and depositing a silicon oxide layer using a plasma enhanced chemical vapor deposition (PECVD) process. The deposition cycle is repeated a specified number of times to form the multi-layer silicon oxide film comprising a plurality of silicon oxide layers formed using the thermal CVD process and a plurality of silicon oxide layers formed using the PECVD process. Each silicon oxide layer formed using the thermal CVD process is adjacent to at least one silicon oxide layer formed using the PECVD process.

    摘要翻译： 在衬底上形成多层氧化硅膜的方法包括执行沉积循环，其包括使用热化学气相沉积（CVD）工艺沉积氧化硅层，并使用等离子体增强化学气相沉积法沉积氧化硅层（ PECVD）过程。 沉积循环重复规定次数以形成包含使用热CVD工艺形成的多个氧化硅层和使用PECVD工艺形成的多个氧化硅层的多层氧化硅膜。 使用热CVD工艺形成的每个氧化硅层与使用PECVD工艺形成的至少一个氧化硅层相邻。

    INVERTABLE PATTERN LOADING WITH DRY ETCH
    59.
    发明申请
    INVERTABLE PATTERN LOADING WITH DRY ETCH 有权
    不可逆图案加载干燥蚀刻

    公开(公告)号：US20110230052A1

    公开(公告)日：2011-09-22

    申请号：US12959155

    申请日：2010-12-02

    申请人： Jing Tang ,  Nitin Ingle ,  Dongqing Yang ,  Shankar Venkataraman

    发明人： Jing Tang ,  Nitin Ingle ,  Dongqing Yang ,  Shankar Venkataraman

    IPC分类号： H01L21/3065

    CPC分类号： H01L21/31116 ,  H01J37/32091

    摘要： A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench.

    摘要翻译： 描述了从窄沟槽和宽沟槽（或开放区域）中蚀刻氧化硅的方法，其允许宽沟槽中的蚀刻比窄沟槽中的蚀刻进一步进行。 该方法包括两个干蚀刻循环。 第一干蚀刻循环涉及低强度或缩写升华步骤，其在窄沟槽中留下固体残留物。 剩余的固体残余物在第二干蚀刻循环期间抑制窄沟槽中的蚀刻进程，允许宽沟槽中的蚀刻超过窄沟槽中的蚀刻。

    Silicon-ozone CVD with reduced pattern loading using incubation period deposition
    60.
    发明授权
    Silicon-ozone CVD with reduced pattern loading using incubation period deposition 失效
    硅 - 臭氧CVD，使用潜伏期沉积减少图案负载

    公开(公告)号：US07994019B1

    公开(公告)日：2011-08-09

    申请号：US12891149

    申请日：2010-09-27

    申请人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

    发明人： Sasha Kweskin ,  Paul Edward Gee ,  Shankar Venkataraman ,  Kedar Sapre

    IPC分类号： H01L21/00

    CPC分类号： H01L21/02164 ,  C23C16/401 ,  C23C16/45523 ,  H01L21/0228

    摘要： Aspects of the disclosure pertain to methods of depositing conformal silicon oxide layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface having heterogeneous materials and/or a heterogeneous pattern density distribution. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on underlying material and pattern density while still being suitable for non-sacrificial applications. Reduction in dependence on pattern density is achieved by terminating deposition near the end of an incubation period. Multiple deposition cycles may be conducted in series since the beneficial nature of the incubation period may repeat after a pause in deposition.

    摘要翻译： 本公开的方面涉及在图案化衬底上沉积保形氧化硅层的方法。 在实施例中，通过将含硅前体和臭氧流入处理室来沉积电介质层，使得跨越具有异质材料的图案化衬底表面和/或异质图案密度分布实现相对均匀的介电生长速率。 根据实施例生长的电介质层的沉积可以降低对下层材料和图案密度的依赖性，同时仍然适用于非牺牲应用。 依靠图案密度的减少是通过在潜伏期结束时终止沉积来实现的。 多个沉积循环可以串联进行，因为在沉积停顿之后潜伏期的有益特性可以重复。