公开(公告)号：US07732919B2

公开(公告)日：2010-06-08

申请号：US12362354

申请日：2009-01-29

申请人： Ichio Shimizu ,  Kenya Kawano ,  Kisho Ashida ,  Yuichi Machida

发明人： Ichio Shimizu ,  Kenya Kawano ,  Kisho Ashida ,  Yuichi Machida

IPC分类号： H01L23/34

CPC分类号： H05K7/04 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/28 ,  H01L24/29 ,  H01L24/36 ,  H01L24/39 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K3/202 ,  H05K3/321 ,  H05K3/3442 ,  H05K2201/0397 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09745 ,  H05K2201/1003 ,  H05K2201/10484 ,  H05K2201/10636 ,  H05K2201/10924 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Coupling reliability of a passive component is improved to increase the reliability of a semiconductor device. A first through hole is formed in a first electrode part of a first plate-like lead, and a second through hole is formed in a second electrode part of a second plate-like lead. As a result, at the first electrode part of the first plate-like lead, one external terminal of the passive component can be coupled to the first electrode parts on both sides of the first through hole while being laid across the first through hole. Also, at the second electrode part of the second plate-like lead, the other external terminal of the passive component can be coupled to the second electrode parts on both sides of the second through hole while being laid across the second through hole. Accordingly, at central portions both in the longitudinal and width directions of the passive component, the passive component is surrounded by sealing members. As a result, thermal stress applied to jointing materials such as solder can be reduced, improving the reliability of the semiconductor device (semiconductor package).

摘要翻译： 改善了无源部件的耦合可靠性，以提高半导体器件的可靠性。 第一通孔形成在第一板状引线的第一电极部分中，第二通孔形成在第二板状引线的第二电极部分中。 结果，在第一板状引线的第一电极部分，无源部件的一个外部端子可以被连接到第一通孔的两侧的第一电极部分，同时跨过第一通孔。 此外，在第二板状引线的第二电极部分，无源部件的另一个外部端子可以在跨过第二通孔而被布置在第二通孔的两侧上的第二电极部件上。 因此，在无源部件的纵向和宽度方向的中心部分处，被动部件被密封部件包围。 结果，可以减少施加到诸如焊料的接合材料的热应力，从而提高半导体器件（半导体封装）的可靠性。

公开(公告)号：US20070210430A1

公开(公告)日：2007-09-13

申请号：US11783919

申请日：2007-04-13

申请人： Hidemasa Kagii ,  Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Masahiko Osaka ,  Takuya Nakajo ,  Keiichi Okawa ,  Hiroi Oka

发明人： Hidemasa Kagii ,  Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Masahiko Osaka ,  Takuya Nakajo ,  Keiichi Okawa ,  Hiroi Oka

IPC分类号： H01L23/02

CPC分类号： H01L23/24 ,  H01L21/52 ,  H01L23/488 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/40225 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.

摘要翻译： 半导体芯片由树脂密封而不覆盖具有功率晶体管的半导体器件的外部端子。 具有功率晶体管的半导体芯片容纳在金属盖的凹部内，而半导体芯片的第一表面上的漏电极经由连接材料接合到凹部的底部。 在与半导体芯片的第一表面相对的第二表面上形成栅电极和源电极，并且栅电极和源电极通过连接材料5b，5c连接金属板端子6G，6S 。 此外，半导体芯片由金属板端子6G，6S的露出的安装面的树脂密封体密封。 金属板端子6G，6S和金属盖的第三部分的安装表面通过连接材料5e，5f和5g与安装板10上的电极接合。

公开(公告)号：US20070176266A1

公开(公告)日：2007-08-02

申请号：US11640161

申请日：2006-12-15

申请人： Kenya Kawano ,  Kisho Ashida ,  Naotaka Tanaka ,  Hiroshi Sato ,  Ichio Shimizu

发明人： Kenya Kawano ,  Kisho Ashida ,  Naotaka Tanaka ,  Hiroshi Sato ,  Ichio Shimizu

IPC分类号： H01L29/06 ,  H01L23/48

CPC分类号： H01L23/49562 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/84 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48247 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84345 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention provides a semiconductor device capable of suppressing degradation in connection reliability due to the decrease in thickness of a conductive adhesive caused by the movement of a connecting plate in a semiconductor device to which a power transistor is mounted. A step is provided in the thin part of the connecting plate connected to a lead post to lock the connecting plate by contacting the step to the tip of the lead post. Alternatively, a groove is provided in the thin part of the connecting plate to lock the connecting plate by connecting the lead post to only the part of the connecting plate on the tip side from the groove.

摘要翻译： 本发明提供一种半导体器件，其能够抑制由于安装有功率晶体管的半导体器件中的连接板的移动引起的导电性粘合剂的厚度的降低导致的连接可靠性的劣化。 在连接到引线柱的​​连接板的薄壁部分设有台阶，以通过使台阶与引线柱的尖端接触来锁定连接板。 或者，在连接板的薄部分中设置有槽，以通过将引线柱仅与槽的尖端侧的连接板的部分连接来锁定连接板。

公开(公告)号：USRE37690E1

公开(公告)日：2002-05-07

申请号：US08448881

申请日：1995-05-24

申请人： Makoto Kitano ,  Sueo Kawai ,  Asao Nishimura ,  Hideo Miura ,  Akihiro Yaguchi ,  Chikako van Koten nee Kitabayashi ,  Ichio Shimizu ,  Toshio Hatsuda ,  Toshinori Ozaki ,  Toshio Hattori ,  Souji Sakata

发明人： Makoto Kitano ,  Sueo Kawai ,  Asao Nishimura ,  Hideo Miura ,  Akihiro Yaguchi ,  Chikako van Koten nee Kitabayashi ,  Ichio Shimizu ,  Toshio Hatsuda ,  Toshinori Ozaki ,  Toshio Hattori ,  Souji Sakata

IPC分类号： H01L23495

CPC分类号： H01L23/49503 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/29007 ,  H01L2224/29111 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2924/3512

摘要： A lead frame and a semiconductor device wherein a through hole is formed in the center of a semiconductor chip-mounting surface of a chip pad at the center of the lead frame, the through hole being tapered or being one which corresponds to a surface area that is greater on the surface of the chip-mounting surface of the chip pad than on the surface of the side opposite to the chip-mounting surface thereof. This prevents the occurrence of cracks in the sealing plastic portion in the step of reflow soldering of the lead frame to the substrate.

摘要翻译： 引线框架和半导体器件，其中在引线框架的中心处的芯片焊盘的半导体芯片安装表面的中心处形成有通孔，该通孔是锥形的，或者是对应于表面积的表面积 在芯片安装面的芯片安装面的表面上比在与芯片安装面相反的一侧的表面上更大。 这防止了在将引线框架回流焊接到基板的步骤中密封塑料部分中出现裂纹。

公开(公告)号：US5194935A

公开(公告)日：1993-03-16

申请号：US647416

申请日：1991-01-29

申请人： Makoto Kitano ,  Asao Nishimura ,  Akihiro Yaguchi ,  Nae Yoneda ,  Ryuji Kohno ,  Sueo Kawai ,  Gen Murakami ,  Ichio Shimizu

发明人： Makoto Kitano ,  Asao Nishimura ,  Akihiro Yaguchi ,  Nae Yoneda ,  Ryuji Kohno ,  Sueo Kawai ,  Gen Murakami ,  Ichio Shimizu

IPC分类号： H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367

CPC分类号： H01L21/565 ,  H01L23/3107 ,  H01L23/3675 ,  H01L2224/48091 ,  H01L2224/48247

摘要： The plastic encapsulated semiconductor device according to the present invention has a semiconductor chip, leads, and members for electrically connecting these parts to each other. A part of leads, the semiconductor chip and the connecting members are encapsulated with a plastic to form a package. The plate type plastic fins formed on the surface of and integrally with the package are divided in two directions perpendicular to each other thereby forming, for example, rows and columns of fins or fin segments, on the package surface. Therefore, the semiconductor device according to the present invention can be molded easily by a transfer molding. It has a high reliability with respect to the prevention of cracks in the plastic, and a low thermal resistance, and is most suitably used to obtain a high-density package mounting structure.

摘要翻译： 根据本发明的塑料封装半导体器件具有半导体芯片，引线和用于将这些部件彼此电连接的部件。 引线，半导体芯片和连接构件的一部分用塑料封装以形成封装。 形成在包装表面上并与包装整体形成的板状塑料翅片在彼此垂直的两个方向上分开，从而在包装表面上形成例如翅片或鳍片的行和列。 因此，根据本发明的半导体器件可以通过传递模塑容易地模制。 它在防止塑料中的裂纹方面具有高的可靠性，并且具有低的热阻，并且最适合用于获得高密度封装安装结构。

公开(公告)号：US5041901A

公开(公告)日：1991-08-20

申请号：US518410

申请日：1990-05-02

申请人： Makoto Kitano ,  Asao Nishimura ,  Akihiro Yaguchi ,  Sueo Kawai ,  Akio Hoshi ,  Ichio Shimizu

发明人： Makoto Kitano ,  Asao Nishimura ,  Akihiro Yaguchi ,  Sueo Kawai ,  Akio Hoshi ,  Ichio Shimizu

IPC分类号： H01L23/50 ,  H01L23/495 ,  H05K3/34

CPC分类号： H01L23/49582 ,  H05K3/3426 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/181 ,  H05K2201/10689 ,  H05K2201/10772 ,  H05K2201/10909 ,  H05K2201/2081 ,  Y02P70/613

摘要： A lead frame having a plurality of inner leads and outer leads, said outer leads being subjected to surface treatment for improving solder wettability at an end portion and to sruface treatment for suppressing solder wettability at least at a portion neighboring to the end portion, or said outer leads being bent 4 times or more, is effective for improving thermal fatigue life and reliability when applied to a semi-conductor device.

摘要翻译： 具有多个内引线和外引线的引线框架，所述外引线经受表面处理以改善端部处的焊料润湿性，以及至少在与端部相邻的部分处抑制焊料润湿性的表面处理，或所述 外引线弯曲4倍以上，适用于半导体器件时，有效提高热疲劳寿命和可靠性。

公开(公告)号：US4907129A

公开(公告)日：1990-03-06

申请号：US286849

申请日：1988-12-20

申请人： Ichio Shimizu

发明人： Ichio Shimizu

IPC分类号： H01L23/50 ,  H01F3/00 ,  H01F7/16 ,  H01L21/60 ,  H01L23/495

CPC分类号： H01L24/85 ,  H01F3/00 ,  H01F7/1607 ,  H01L23/49544 ,  H01L24/78 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/351

摘要： A lead frame and an electronic device incorporating the lead frame wherein the lead frame includes a chip support and a plurality of leads arranged around the chip support with each of the plurality of leads having one end disposed proximate to the chip support. The one end of at least one of the plurality of leads includes a first lead portion extending in a direction toward the chip support and a second lead portion contiguous with the first lead portion. The second lead portion extends in a direction away from the chip support so that the one of the lead has a bent shape.