公开(公告)号：US11721733B2

公开(公告)日：2023-08-08

申请号：US17366934

申请日：2021-07-02

Applicant: LONGITUDE FLASH MEMORY SOLUTIONS LTD.

Inventor： Igor Polishchuk ,  Sagy Charel Levy ,  Krishnaswamy Ramkumar

IPC: H01L21/28 ,  H01L29/423 ,  G11C16/04 ,  H01L29/792 ,  H01L29/51 ,  H01L29/66 ,  B82Y10/00 ,  H10B41/40 ,  H10B43/00 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50 ,  H01L29/49 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/4234 ,  B82Y10/00 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02532 ,  H01L21/02595 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H10B41/40 ,  H10B43/00 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50

Abstract: Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed.

公开(公告)号：US11721723B2

公开(公告)日：2023-08-08

申请号：US17321046

申请日：2021-05-14

Applicant: Intel Corporation ,  Technishce Universiteit Delft

Inventor： Kanwaljit Singh ,  James S. Clarke ,  Menno Veldhorst ,  Lieven Mark Koenraad Vandersypen

IPC: H01L29/12 ,  G06N10/00 ,  H01L29/66 ,  B82Y10/00 ,  B82Y40/00

CPC classification number: H01L29/122 ,  G06N10/00 ,  H01L29/66977 ,  B82Y10/00 ,  B82Y40/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

公开(公告)号：US11721521B2

公开(公告)日：2023-08-08

申请号：US17697842

申请日：2022-03-17

Applicant: ASML Netherlands B.V.

Inventor： Weiming Ren ,  Xuedong Liu ,  Xuerang Hu ,  Zhong-wei Chen

IPC: H01J37/31 ,  H01J37/14 ,  H01J37/30 ,  H01J37/28 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/317 ,  H01J37/147

CPC classification number: H01J37/3177 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/1471 ,  H01J37/1472 ,  H01J37/28 ,  H01J37/3007 ,  H01J2237/151 ,  H01J2237/1501 ,  H01J2237/1508 ,  H01J2237/2446 ,  H01J2237/2448 ,  H01J2237/24475 ,  H01J2237/2804 ,  H01J2237/2817

Abstract: The present disclosure proposes a crossover-forming deflector array of an electro-optical system for directing a plurality of electron beams onto an electron detection device. The crossover-forming deflector array includes a plurality of crossover-forming deflectors positioned at or at least near an image plane of a set of one or more electro-optical lenses of the electro-optical system, wherein each crossover-forming deflector is aligned with a corresponding electron beam of the plurality of electron beams.

公开(公告)号：US11720084B2

公开(公告)日：2023-08-08

申请号：US17802742

申请日：2021-09-22

Applicant: CBN Nano Technologies Inc.

Inventor： James F. Ryley, III ,  Mark N. Jobes ,  James MacArthur ,  Jeffrey E. Semprebon

IPC: G05B19/4155 ,  B82Y10/00 ,  G06F5/01

CPC classification number: G05B19/4155 ,  B82Y10/00 ,  G06F5/01 ,  G05B2219/33291

Abstract: Logic mechanisms operate to define the position of at least one mechanical output based on the position of at least one mechanical input. Some mechanisms are configured to determine, based on the input position(s), whether a path to transmit motion to an output exists or does not exist. Some mechanisms are configured to determine, based on the input position(s), whether or not motion of a driven element can be accommodated without moving an output. Some mechanisms are configured to determine, based on the input position(s), whether or not one or more elements are constrained to transmit motion to an output.

公开(公告)号：US11715028B2

公开(公告)日：2023-08-01

申请号：US17746544

申请日：2022-05-17

Applicant: IONQ, INC.

Inventor： Yunseong Nam ,  Reinhold Blumel ,  Nikodem Grzesiak

IPC: G06N10/00 ,  G21K1/00 ,  H01S3/09 ,  B82Y10/00 ,  H01J49/00 ,  H04B10/70

CPC classification number: G06N10/00 ,  B82Y10/00 ,  G21K1/003 ,  H01J49/0072 ,  H01S3/09 ,  H04B10/70

Abstract: A method of performing a computation using a quantum computer includes generating a plurality of laser pulses used to be individually applied to each of a plurality of trapped ions that are aligned in a first direction, each of the trapped ions having two frequency-separated states defining a qubit, and applying the generated plurality of laser pulses to the plurality of trapped ions to perform simultaneous pair-wise entangling gate operations on the plurality of trapped ions. Generating the plurality of laser pulses includes adjusting an amplitude value and a detuning frequency value of each of the plurality of laser pulses based on values of pair-wise entanglement interaction in the plurality of trapped ions that is to be caused by the plurality of laser pulses.

公开(公告)号：US20230214319A9

公开(公告)日：2023-07-06

申请号：US16460051

申请日：2019-07-02

Applicant: EUROPEAN MOLECULAR BIOLOGY LABORATORY

Inventor： Nick Goldman ,  John Birney

IPC: G06F12/02 ,  B82Y10/00 ,  G06N3/12 ,  G16B50/40 ,  G16B50/50 ,  G16B30/00

CPC classification number: G06F12/023 ,  B82Y10/00 ,  G06N3/123 ,  G16B50/40 ,  G16B50/50 ,  G16B30/00 ,  G06F2212/1032

Abstract: A method for storage of an item of information (210) is disclosed. The method comprises encoding bytes (720) in the item of information (210), and representing using a schema the encoded bytes by a DNA nucleotide to produce a DNA sequence (230). The DNA sequence (230) is broken into a plurality of overlapping DNA segments (240) and indexing information (250) added to the plurality of DNA segments. Finally, the plurality of DNA segments (240) is synthesized (790) and stored (795).

公开(公告)号：US20230209830A1

公开(公告)日：2023-06-29

申请号：US18102917

申请日：2023-01-30

Applicant: LONGITUDE FLASH MEMORY SOLUTIONS LTD.

Inventor： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

IPC: H10B43/30 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/105 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H10B43/27 ,  H10B43/40 ,  H10B99/00 ,  B82Y10/00

CPC classification number: H10B43/30 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/105 ,  H01L21/31116 ,  H01L21/32135 ,  H01L29/1033 ,  H01L29/42352 ,  H01L29/4925 ,  H10B43/27 ,  H10B43/40 ,  H10B99/00 ,  B82Y10/00

Abstract: An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

公开(公告)号：US11688735B2

公开(公告)日：2023-06-27

申请号：US17341559

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： James S. Clarke ,  Nicole K. Thomas ,  Zachary R. Yoscovits ,  Hubert C. George ,  Jeanette M. Roberts ,  Ravi Pillarisetty

IPC: H01L29/775 ,  H10N69/00 ,  H01L27/088 ,  G06N10/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/778 ,  B82Y10/00

CPC classification number: H01L27/088 ,  G06N10/00 ,  H01L21/823456 ,  H01L29/66977 ,  H01L29/778 ,  H10N69/00 ,  B82Y10/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

公开(公告)号：US11682735B2

公开(公告)日：2023-06-20

申请号：US17231120

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hun Lee ,  Dong Woo Kim ,  Dong Chan Suh ,  Sun Jung Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L29/786 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/068 ,  H01L29/66742 ,  H01L29/78651 ,  H01L29/78684 ,  Y10S977/762 ,  Y10S977/765 ,  Y10S977/938

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

公开(公告)号：US20230187552A1

公开(公告)日：2023-06-15

申请号：US18164965

申请日：2023-02-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： I-Sheng CHEN ,  Tzu-Chiang CHEN ,  Cheng-Hsien WU ,  Ling-Yen YEH ,  Carlos H. DIAZ

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/768 ,  H01L27/092 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/40 ,  H01L27/06 ,  H01L29/775 ,  H01L21/822 ,  H01L29/08 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L21/76877 ,  H01L29/66484 ,  H01L29/6656 ,  H01L27/0924 ,  B82Y10/00 ,  H01L29/42392 ,  H01L29/401 ,  H01L27/0688 ,  H01L29/775 ,  H01L21/8221 ,  H01L29/0847 ,  H01L29/0653 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/66545 ,  H01L29/66439 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/82345 ,  H01L21/823412

Abstract: A multi-gate semiconductor device includes a plurality of nanostructures vertically stacked over a substrate, a gate dielectric layer wrapping around the plurality of nanostructures, a gate conductive structure over the gate dielectric layer, and a first insulating spacer alongside the gate conductive structure and over the plurality of nanostructures. The first insulating spacer is in direct contact with the gate conductive structure and the gate dielectric layer.