公开(公告)号：US06194990B1

公开(公告)日：2001-02-27

申请号：US09268956

申请日：1999-03-16

Applicant: Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

Inventor： Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

IPC: H01C101

CPC classification number: H05K1/167 ,  H05K3/0023 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09845 ,  H05K2201/10045 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: A thin-film metal resistor (44) suitable for a multilayer printed circuit board (12), and a method for its fabrication. The resistor (44) generally has a multilayer construction, with the individual layers (34, 38) of the resistor (44) being self-aligned with each other so that a negative mutual inductance is produced that very nearly cancels out the self-inductance of each resistor layer (34, 38). As a result, the resistor (44) has a very low net parasitic inductance. In addition, the multilayer construction of the resistor (44) reduces the area of the circuit board (12) required to accommodate the resistor (44), and as a result reduces the problem of parasitic interactions with other circuit elements on other layers of the circuit board (12).

Abstract translation: 适用于多层印刷电路板（12）的薄膜金属电阻（44）及其制造方法。 电阻器（44）通常具有多层结构，其中电阻器（44）的各个层（34,38）彼此自对准，使得产生负的互感，其几乎抵消了自感 的每个电阻层（34,38）。 结果，电阻器（44）具有非常低的净寄生电感。 此外，电阻器（44）的多层结构减小了容纳电阻器（44）所需的电路板（12）的面积，结果减少了与其他层上的其它电路元件的寄生相互作用的问题 电路板（12）。

公开(公告)号：US5621619A

公开(公告)日：1997-04-15

申请号：US445237

申请日：1995-05-19

Applicant: Lewis L. Seffernick ,  Neal F. Thomas

Inventor： Lewis L. Seffernick ,  Neal F. Thomas

IPC: H01C1/01 ,  H01C13/02 ,  H01C17/00 ,  H01C17/28 ,  H05K3/30 ,  H05K3/34 ,  H01R9/00

CPC classification number: H05K3/303 ,  H01C13/02 ,  H01C17/006 ,  H05K3/3442 ,  H05K2201/09909 ,  H05K2201/10022 ,  H05K2201/10045 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10696 ,  H05K2201/10984 ,  H05K2203/167 ,  H05K3/3452 ,  Y02P70/613

Abstract: A resistor network is disclosed which is suited for surface mount which does not incorporate wire terminations. The network is fabricated entirely from cermet, ceramic, and solder, yet will absorb thermal stresses normally associated with circuitry energization when properly mounted upon a substrate. This is accomplished by controlling the formation of solder bumps and simultaneously controlling the mounted distance between those bumps and a wiring substrate upon which the network is mounted. Additionally, the network may be formed to be either a SIP or DIP configuration, depending upon whether an additional groove is incorporated into the termination side of the substrate. Two alternative embodiments are also disclosed which incorporate various features of the invention.

Abstract translation: 公开了一种适用于不包含电线终端的表面安装的电阻器网络。 网络完全由金属陶瓷，陶瓷和焊料制成，但是当正确安装在基板上时，它将吸收通常与电路通电相关的热应力。 这是通过控制焊料凸点的形成并同时控制这些凸起之间的安装距离和安装网络的布线基板来实现的。 另外，取决于附加的沟槽是否被结合到衬底的端接侧中，网络可以形成为SIP或DIP配置。 还公开了两个替代实施例，其包括本发明的各种特征。

公开(公告)号：US4331949A

公开(公告)日：1982-05-25

申请号：US175954

申请日：1980-08-07

Applicant: Yoshii Kagawa

Inventor： Yoshii Kagawa

IPC: H01C7/00 ,  H01C13/02 ,  H01L27/01 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H01C1/012

CPC classification number: H05K1/167 ,  H01C13/02 ,  H01C7/003 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/10045

Abstract: A thick film printed circuit in which a plurality of electrode patterns are disposed with approximately equal spaced intervals between one another, resistance patterns having approximately equal widths are mounted between adjacent electrode patterns of said plurality of electrode patterns, and an identical shaped resistance pattern to said resistance pattern is provided so as to align in parallel with at least one of said resistance patterns, whereby exact divided potential can be obtained.

Abstract translation: 一种厚膜印刷电路，其中多个电极图案彼此间隔开大致相等的间隔设置，具有大致相等宽度的电阻图案安装在所述多个电极图案的相邻电极图案之间，并且与所述 提供电阻图案以与所述电阻图案中的至少一个平行地对准，从而可以获得精确的分割电位。

公开(公告)号：US4127934A

公开(公告)日：1978-12-05

申请号：US813069

申请日：1977-07-05

Applicant: John E. Bartley ,  Orville R. Penrod ,  Lawrence D. Radosevich

Inventor： John E. Bartley ,  Orville R. Penrod ,  Lawrence D. Radosevich

IPC: H01L23/50 ,  H01G4/236 ,  H01L23/498 ,  H05K1/03 ,  H05K1/09 ,  H05K1/14 ,  H05K1/16 ,  H05K3/34 ,  H05K3/40 ,  H05K3/32

CPC classification number: H05K3/3405 ,  H01L23/49811 ,  H05K1/167 ,  H01L2924/0002 ,  H05K1/0272 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/141 ,  H05K1/162 ,  H05K2201/09163 ,  H05K2201/10045 ,  H05K2201/1034 ,  H05K2201/10924 ,  H05K3/403 ,  Y10T29/49101 ,  Y10T29/49151 ,  Y10T29/53174

Abstract: An electrical circuit device having a substrate including circuit components on at least one side thereof and a plurality of through openings in the substrate. Terminal leads are positioned in the openings each with a deformation intermediate the ends of the leads and spaced internally of the opening from a soldered area at the juncture of the exposed portion of the leads and the termination edge of the substrate. Two methods of assembly of leads to the substrate are also disclosed.

Abstract translation: 一种电路装置，其具有在至少一个侧面上包括电路元件的基板和该基板中的多个通孔。 端子引线定位在开口中，每个开口具有在引线的端部之间的中心的变形，并且在引线的暴露部分和基板的终端边缘的接合处的焊接区域处与开口的内部隔开。 还公开了将引线组装到衬底的两种方法。

公开(公告)号：US20240032196A1

公开(公告)日：2024-01-25

申请号：US18043356

申请日：2020-09-07

Applicant: GOERTEK TECHNOLOGY CO., LTD.

Inventor： Kenichiro KODAMA

IPC: H05K1/14 ,  H05K1/02

CPC classification number: H05K1/142 ,  H05K1/025 ,  H05K1/028 ,  H05K2201/10098 ,  H05K2201/10196 ,  H05K2201/10045

Abstract: An electronic device includes a first circuit operating on a first signal of a first frequency and a second circuit operating on a second signal of a second frequency. The first signal is different from the second signal, and the first circuit and the second circuit share a first component. The first component functions as an antenna for the second circuit, which reduces space occupied by a dedicated or independent antenna and achieves smaller size and better industrial design for the electronic device.

公开(公告)号：US11653441B2

公开(公告)日：2023-05-16

申请号：US16951695

申请日：2020-11-18

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Julien Didion ,  Thierry Lapergue

IPC: H05K1/02 ,  H04B1/16 ,  H05K1/18

CPC classification number: H05K1/025 ,  H04B1/16 ,  H05K1/181 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10045 ,  H05K2201/10098

Abstract: A device includes a printed circuit board substrate, an antenna connected to the printed circuit board substrate, an amplifier connected to the printed circuit board substrate, and a matching track having a first end electrically connected to an input of the amplifier and a second end electrically connected to an output of the antenna. The matching track has an outgrowth that is symmetrical along a median axis of the outgrowth. The matching track is rectilinear and has a constant width over an initial part extending between the widening area and the first end. A median axis of the initial part and the median axis of the outgrowth form an angle comprised between 60 and 120°.

公开(公告)号：US09685273B2

公开(公告)日：2017-06-20

申请号：US15051648

申请日：2016-02-23

Applicant: ROHM CO., LTD.

Inventor： Hiroki Yamamoto ,  Keishi Watanabe ,  Hiroshi Tamagawa

IPC: H01L27/00 ,  H01G4/30 ,  H01L23/522 ,  H01L27/10 ,  H01L27/24 ,  H01L23/00 ,  H01G4/40 ,  H01L29/66 ,  H01L29/94 ,  H01G2/06 ,  H05K1/11 ,  H05K1/16 ,  H05K1/18 ,  H01L21/66 ,  H01L27/06 ,  H01G4/005 ,  H01G4/228 ,  H01G4/232

CPC classification number: H01G4/30 ,  H01G2/06 ,  H01G4/005 ,  H01G4/228 ,  H01G4/232 ,  H01G4/40 ,  H01L22/14 ,  H01L22/20 ,  H01L23/5223 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0676 ,  H01L27/101 ,  H01L27/2409 ,  H01L28/40 ,  H01L29/66189 ,  H01L29/94 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/0002 ,  H05K1/111 ,  H05K1/162 ,  H05K1/18 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/10045 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

公开(公告)号：US09215807B2

公开(公告)日：2015-12-15

申请号：US13626858

申请日：2012-09-25

Applicant: Shawn X. Arnold ,  Jeffrey M. Thoma

Inventor： Shawn X. Arnold ,  Jeffrey M. Thoma

IPC: H05K1/14 ,  H05K1/02 ,  H05K1/11 ,  H05K3/36

CPC classification number: H05K1/141 ,  H05K1/0231 ,  H05K1/111 ,  H05K3/366 ,  H05K2201/049 ,  H05K2201/10045 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49133

Abstract: The described embodiments relate generally to electronic components and more specifically to a capacitor array that can increase component density on a printed circuit board and reduce a distance to a ground plane. An array of capacitors can be formed by coupling a group of capacitors on their sides interspersed with interposer boards. The resulting configuration can increase component density and reduce an amount of resistance and effective series inductance between a set of power decoupling capacitors and an integrated circuit.

Abstract translation: 所描述的实施例一般涉及电子部件，更具体地涉及可以增加印刷电路板上的部件密度并减小到接地平面的距离的电容器阵列。 一组电容器可以通过将一组电容器连接在插入有插入板的侧面上形成。 所得到的配置可以增加组件密度并减少一组功率去耦电容器和集成电路之间的电阻和有效串联电感量。

公开(公告)号：US08461463B2

公开(公告)日：2013-06-11

申请号：US13080783

申请日：2011-04-06

Applicant: Noboru Kato ,  Jun Sasaki ,  Katsumi Taniguchi

Inventor： Noboru Kato ,  Jun Sasaki ,  Katsumi Taniguchi

IPC: H05K1/16

CPC classification number: H05K1/186 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/645 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/19106 ,  H05K1/141 ,  H05K1/165 ,  H05K3/284 ,  H05K2201/09481 ,  H05K2201/10045 ,  H05K2203/1316

Abstract: A composite module is obtained which enables high-density mounting of components without increasing its size. A composite module includes a main substrate which is a multilayer circuit board, a sub-substrate mounted on a lower surface of the main substrate, a sealing layer arranged on the lower surface of the main substrate to cover the sub-substrate, the sealing layer defining a mount surface arranged to be mounted on a mount board, and terminal electrodes disposed on the mount surface. The terminal electrodes include at least one first terminal electrode drawn directly from the main substrate and at least one second terminal electrode drawn directly from the sub-substrate.

Abstract translation: 获得了组合模块，其可以在不增加其尺寸的情况下实现组件的高密度安装。 复合模块包括作为多层电路板的主衬底，安装在主衬底的下表面上的子衬底，设置在主衬底的下表面以覆盖副衬底的密封层，密封层 限定安装在安装板上的安装表面和设置在安装表面上的端子电极。 端子电极包括从主衬底直接绘制的至少一个第一端子电极和直接从该辅助衬底引出的至少一个第二端子电极。

公开(公告)号：US20110182039A1

公开(公告)日：2011-07-28

申请号：US13080783

申请日：2011-04-06

Applicant: Noboru KATO ,  Jun SASAKI ,  Katsumi TANIGUCHI

Inventor： Noboru KATO ,  Jun SASAKI ,  Katsumi TANIGUCHI

IPC: H05K1/14

CPC classification number: H05K1/186 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/645 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/19106 ,  H05K1/141 ,  H05K1/165 ,  H05K3/284 ,  H05K2201/09481 ,  H05K2201/10045 ,  H05K2203/1316

Abstract: A composite module is obtained which enables high-density mounting of components without increasing its size. A composite module includes a main substrate which is a multilayer circuit board, a sub-substrate mounted on a lower surface of the main substrate, a sealing layer arranged on the lower surface of the main substrate to cover the sub-substrate, the sealing layer defining a mount surface arranged to be mounted on a mount board, and terminal electrodes disposed on the mount surface. The terminal electrodes include at least one first terminal electrode drawn directly from the main substrate and at least one second terminal electrode drawn directly from the sub-substrate.

Abstract translation: 获得了组合模块，其可以在不增加其尺寸的情况下实现组件的高密度安装。 复合模块包括作为多层电路板的主衬底，安装在主衬底的下表面上的子衬底，设置在主衬底的下表面以覆盖副衬底的密封层，密封层 限定安装在安装板上的安装表面和设置在安装表面上的端子电极。 端子电极包括从主衬底直接绘制的至少一个第一端子电极和直接从该辅助衬底引出的至少一个第二端子电极。